Prof. Sangwan Kim's publication
Journal Conference Patent Thesis Award
International Conference
[109] Changyoung Song, Jehyeok Jung, Kihoon Kim, Sangwan Kim and Sihyun Kim, “Impact of electrode work function variation on sensing margin in 1T-1C FeRAM,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, pp. 872-873, Jan. 19-22, 2025.
[108] Jongho Shin, Jinsung Lee, Seongju Cho, Jiwon Han, Sangwan Kim and Sihyun Kim, “Analysis of self heating effect in advanced gate-all-around structure,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, p. 879, Jan. 19-22, 2025.
[107] Sanghyeok Seo, Jeonghwan Kim, Seungmin Kang, Sangwan Kim and Sihyun Kim, “BEOL compatible Hf0.5Zr0.5O2 film using ZrO2 seed layer,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, pp. 877-878, Jan. 19-22, 2025.
[106] Jinhong Lee, Jae Yeon Park and Sangwan Kim, “Investigation of concave and convex structure in 3D-NAND flash memory,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, p. 863, Jan. 19-22, 2025.
[105] Changmin Chae, Dongseok Oh, Hyungju Noh and Sangwan Kim, “Analysis of parasitic resistance in vertically stacked GAA MOSFET with wrap around contact,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, p. 862, Jan. 19-22, 2025.
[104] Dongseok Oh, Changmin Chae, Hyungju Noh and Sangwan Kim, “Impact of source/drain doping concentrations on the electrical characteristics of vertically stacked GAA MOSFETs with wrap around contact,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, p. 861, Jan. 19-22, 2025.
[103] Minse Kim, Taegun Kim, Dong Keun Lee and Sangwan Kim, “Optimization of sidewall spacer in MFMIS FeFET for enhanced memory window and endurance,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, pp. 859-860, Jan. 19-22, 2025.
[102] Jiwon Han, Hyunho Ahn, Dongseok Kwon, Sangwan Kim and Sihyun Kim, “Nanowire JLFET-integrated ternary-CMOS for optimized static noise margin operation,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, pp. 740-741, Jan. 19-22, 2025.
[101] Hyeok Jun You, Kihoon Kim, Dongseok Kwon, Sangwan Kim and Sihyun Kim, “Optimization of array bias scheme for 1T-nC FeRAM,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, pp. 742-743, Jan. 19-22, 2025.
[100] Jinhwan Jung, Seonggeun Kim, Sihyun Kim and Sangwan Kim, “A novel ferroelectric field-effect transistor (FeFET) for a reliable multi-bit operation,” International Conference on Electronics, Information and Conference (ICEIC), Osaka, Japan, pp. 744-745, Jan. 19-22, 2025.
[99] Dong Keun Lee, Hyunho Ahn, Sihyun Kim, and Sangwan Kim, “Dual-channel MOSFET-based ternary-CMOS inverter,” International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE), Jeju, Korea, Nov. 26, 2024.
[98] Jae Yeon Park, Jaekyun Son, Dong Keun Lee, and Sangwan Kim, “Demonstration of neuron device using charge trap flash memory,” International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE), Jeju, Korea, Nov. 25, 2024.
[97] Yelim Jeon, Hyungju Noh, Sihyun Kim, and Sangwan Kim, “Impact of work function variation in gate-injection flash (GI Flash),” International SoC Design Conference (ISOCC), Sapporo, Japan, pp. 38, Aug. 19-22, 2024.
[96] Seungmin Kang, Sangwan Kim, and Sihyun Kim, “Write bias scheme optimization of ferroelectric field-effect-transistor (FeFET) synapse for accurate on-chip training ,” International SoC Design Conference (ISOCC), Sapporo, Japan, pp. 38, Aug. 19-22, 2024.
[95] Kihoon Kim, Hyeokjun You, Sangwan Kim, and Sihyun Kim, “A highly integrable 3D n-capacitor-stacked ferroelectric RAM,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Gangneung, Korea, pp. 73-74, Jul. 7-10, 2024.
[94] Heebum Kang, Seungmin Kang, Sangwan Kim, and Sihyun Kim, “Vertical ferroelectric-metal field-effect-transistor analog synapse device for low power deep neural network training,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Gangneung, Korea, pp. 180-181, Jul. 7-10, 2024.
[93] Sunwoo Lee, Seungwon Go, and Sangwan Kim, “Investigation on the bias scheme for AND array operation based on ferroelectric tunnel field-effect transistor,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Gangneung, Korea, pp. 144-145, Jul. 7-10, 2024.
[92] Jaewon Jang, Shinhee Kim, Hyungju Noh, Sihyun Kim, and Sangwan Kim, “Analysis of hump characteristics induced by band-to-band tunneling in floating-body n-MOSFET with ultra-shallow source/drain junction depth,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Gangneung, Korea, pp. 197-198, Jul. 7-10, 2024.
[91] Hyungju Noh, Yelim Jeon, Sihyun Kim, and Sangwan Kim, “Investigation of the memory characteristics in the gate-injection ferroelectric metal/oxide/semiconductor (MOS) capacitors,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Gangneung, Korea, pp. 84-85, Jul. 7-10, 2024.
[90] Hyunho Ahn, Jang Hyun Kim, Sihyun Kim, and Sangwan Kim, “CMOS comparable ternary inverter with high operation stability,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Gangneung, Korea, pp. 184-186, Jul. 7-10, 2024.
[89] Jaekyun Son, Jae Yeon Park, Tae-Hyeon Kim, Sihyun Kim and Sangwan Kim, “Investigation on electron back tunneling effect in charge trap flash memory with SiO2-Si3N4 (ON) gate dielectric,” International Conference on Electronics, Information and Conference (ICEIC), Taipei, Taiwan, pp. 420-422, Jan. 28-31, 2024.
[88] Heebum Kang, Seungwon Go, Seungmin Kang, Kihoon Kim, Jiwon Han, Tae-Hyeon Kim, Sangwan Kim and Sihyun Kim, “Vertical-ferroelectric-metal field-effect transistor(V-FeMFET) for low-power non-volatile memory,” International Conference on Electronics, Information and Conference (ICEIC), Taipei, Taiwan, pp. 416-419, Jan. 28-31, 2024.
[87] Taegun Kim, Dong Keun Lee, Sihyun Kim, and Sangwan Kim, “A simulation study about the memory operation of 3D-stacked capacitor-less 1T DRAM cells based on ferroelectric field-effect transistors (FeFETs),” International SoC Design Conference (ISOCC), Jeju, Korea, pp. 135-136, Oct. 25-28, 2023.
[86] Nam seong Kim, Sangwan Kim, Hyeokyun Lee, Woo Young Jung, Young Soo Han, Changseop Kim, Hyungju Noh, Jaewon Jang, and Seon Woo Bong, “Analysis of flat-top nanosecond green laser annealing process for semiconductor Si wafers,” International Congress on Applications of Lasers & Electro-Optics (ICALEO), Chicago, IL, USA, Oct. 16-19, 2023.
[85] Seonggeun Kim, Seungwon Go, Hyungju Noh, Dong Keun Lee, and Sangwan Kim, “Study about thermal stability in ferroelectric Hf0.5Zr0.5O2 film with Al2O3 layer,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Yokohama, Japan, pp. 96-97, Jul. 10-11, 2023.
[84] Seungwon Go, Hyungju Noh, Dong Keun Lee, Seonggeun Kim, Un-hyun Im, Hojoong Lee, and Sangwan Kim, “Investigation on ferroelectricity in Zr-doped HfO2 (HZO) based laminated structure with TEMA-Hf and Cp-Zr,” Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Yokohama, Japan, pp. 30-31, Jul. 10-11, 2023.
[83] Hyung Ju Noh, Seungwon Go, Sangwan Kim, “The effect of CMOS/CFE in MFMIS-based ferroelectric tunnel field-effect transistor (FeTFET),” International SoC Design Conference (ISOCC), Gangneung, Korea, pp. 233-234, Oct. 19-21, 2022.
[82] Sangwan Kim, “Study about self-heating effects in gate-all-around nanowire transistors,” China Semiconductor Technology International Conference (CSTIC), Shanghai, China, Jun. 14-Jul. 12, 2022. [Invited]
[81] Dongkeun Lee and Sangwan Kim, “The effect of ferroelectric dynamic behavior on negative capacitance field-effect transistor-based SRAM,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Online, Korea, pp. 159-160, Jul. 7-8, 2022.
[80] Seungwon Go, Jae Yeon Park, Shinhee Kim, Hyung Ju Noh, Dong Keun Lee, So Ra Park, and Sangwan Kim, “Investigation on the effect of gate overlap/underlap on the 1T DRAM cell,” International Conference on Electronics, Information and Communication (ICEIC), Jeju, Korea, pp. 791 – 793, Feb. 6-9, 2022.
[79] Dongkeun Lee, Seungwon Go, Jae Yeon Park, Shinhee Kim, Hyung Ju Noh, So Ra Park, and Sangwan Kim, “The effect of ferroelectric dynamic behavior on negative capacitance field-effect transistor inverter,” International Conference on Electronics, Information and Communication (ICEIC), Jeju, Korea, pp. 783 – 786, Feb. 6-9, 2022.
[78] Jae Yeon Park, Shinhee Kim, Seungwon Go, and Sangwan Kim , “Negative capacitance field-effect transistor with hetero-metal-gate to suppress the reverse drain-induced barrier lowering,” International Microprocesses and Nanotechnology Conference (MNC), Online, Japan, pp. 22-7, Oct. 26-29, 2021.
[77] Hyung Ju Noh and Sangwan Kim , “Effect of body thickness on the electrical characteristics of source-pocket (PNPN) tunnel field-effect transistor (TFET),” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Online, Japan, pp. 144-145, Aug. 26-27, 2021.
[76] Joonho Park, Moonjung Choi, and Sangwan Kim , “Study of MFIM structure-based ferroelectric tunnel junction according to dielectric thickness and annealing temperature,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Online, Japan, pp. 97-98, Aug. 26-27, 2021.
[75] Shinhee Kim and Sangwan Kim , “Negative differential resistance (NDR) in hetero-gate-dielectric negative capacitance tunnel field-effect transistor (NCTFET),” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Online, Japan, pp. 48-49, Aug. 26-27, 2021.
[74] Seungwon Go and Sangwan Kim , “Analysis of work-function variation effects on a negative capacitance tunnel field-effect transistor,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Online, Japan, pp.21-22, Aug. 26-27, 2021.
[73] Seok Jung Kang, Seungwon Go, Jang Hyun Kim, and Sangwan Kim , “Investigation on the generation mechanisms of interface traps during hot carrier stress,” International Conference on Electronics, Information and Communication (ICEIC), Jeju, Korea, pp. 672-675, Jan. 31- Feb. 3, 2021.
[72] Shinhee Kim and Sangwan Kim , “Simulation study about negative capacitance effects on recessed channel tunnel FET,” International Microprocesses and Nanotechnology Conference (MNC), Osaka, Japan, pp. 2020-22-25, Nov. 9-12, 2020.
[71] Young Suh Song, Jang Hyun Kim, Sangwan Kim , Garam Kim, Hyun-Min Kim, Hyunwoo Kim, Junsu Yu, and Byung-Gook Park, “Improvement of self-heating effect in Ge vertically stacked gate-all-around pMOSFET,” International Microprocesses and Nanotechnology Conference (MNC), Osaka, Japan, pp. 2020-22-20, Nov. 9-12, 2020.
[70] Junho Park, Unhyun Im, and Sangwan Kim , “Study on the electrical characteristics of MOSFET with VO2 layer stacked on the gate oxide,” International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE), Jeju, Korea, pp. A20200715-3446, Nov. 1-4, 2020.
[69] Seunghyun Yun, Jeongmin Oh, Seokjung Kang, and Sangwan Kim , “A novel tunnel field-effect transistor (TFET) for high current drivability,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Busan, Korea, pp. 237-238, Jul. 1-3, 2019.
[68] Jang Hyun Kim, Un-Hyun Im, and Sangwan Kim , “Study on nonlinear output characteristics of tunnel field-effect transistor,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Busan, Korea, pp. 213-214, Jul. 1-3, 2019.
[67] Shinhee Kim, Hyun Ho Ahn, and Sangwan Kim , “Temperature dependency of ferroelectric properties in HfZrO capacitors,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Busan, Korea, pp. 154-155, Jul. 1-3, 2019.
[66] KyungJin Rim and Sangwan Kim , “Design guideline of the negative capacitance field-effect transistor (NCFET) depending on Landau parameters,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Busan, Korea, pp. 70-71, Jul. 1-3, 2019.
[65] Ryoongbin Lee, Junil Lee, Sangwan Kim , Kitae Lee, Sihyun Kim, Soyoun Kim, Yunho Choi, and Byung-Gook Park, “Ge condensation process for high on/off ratio of SiGe gate-all-around nanowire tunnel field-effect transistor,” IEEE Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, pp. 51-52, Jun. 9-10, 2019.
[64] Kitae Lee, Junil Lee, Sihyun Kim, Soyoun Kim, Munhyeon Kim, Sangwan Kim , and Byung-Gook Park, “Analysis on fully depleted negative capacitance field-effect transistor (NCFET) based on electrostatic potential difference,” IEEE Electron Devices Technology and Manufacturing (EDTM) Conference , Singapore, pp. 422-424, Mar. 12-15, 2019.
[63] Munhyeon Kim, Kitae Lee, Sihyun Kim, Soyoun Kim, Sangwan Kim , and Byung-Gook Park, “Novel stacked floating fin structure gate-all-around field-effect transistor for design and power optimization,” IEEE Electron Devices Technology and Manufacturing (EDTM) Conference , Singapore, pp. 136-138, Mar. 12-15, 2019.
[62] Soyoun Kim, Sihyun Kim, Kitae Lee, Munhyeon Kim, Ryoongbin Lee, Sangwan Kim , and Byung-Gook Park, “Accurate effective width extraction methods for sub-10nm multi-gate MOSFETs through capacitance measurement,” IEEE Electron Devices Technology and Manufacturing (EDTM) Conference , Singapore, pp. 115-117, Mar. 12-15, 2019.
[61] Sihyun Kim, Kitae Lee, Munhyeon Kim, Soyoun Kim, Suhyeon Kim, Sangwan Kim , and Byung-Gook Park, “Channel thickness and interfacial trap variation induced by selective-channel-etching in stacked gate-all-around MOSFETs having multi-channel-width” International Microprocesses and Nanotechnology Conference (MNC), Sapporo, Japan, p. 16P-11-112L, Nov. 13-16, 2018.
[60] Seong Su Shin, Jang Hyun Kim, and Sangwan Kim , “L-shaped TFET with stacked-gates to suppress the corner effect,” International Microprocesses and Nanotechnology Conference (MNC), Sapporo, Japan, p. 16P-11-107L, Nov. 13-16, 2018.
[59] Soyoun Kim, Sihyun Kim, Kitae Lee, Munhyeon Kim, Suhyeon Kim, Junil Lee, Ryoongbin Lee, Sangwan Kim , Y. Yasuda-Masuoka, and Byung-Gook Park, “Ultra-low leakage technology for sub 10nm FinFET and GAAFET by optimized anti punch-through implantation” International Microprocesses and Nanotechnology Conference (MNC), Sapporo, Japan, p. 15P-7-27, Nov. 13-16, 2018.
[58] Ryoongbin Lee, Junil Lee, Sangwan Kim , Sihyun Kim, Euyhwan Park, and Byung-Gook Park, “Variation effect of Ge concentration in SiGe channel of vertically-stacked tunnel field-effect transistor (TFET),” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Bangkok, Thailand, pp. 82-85, Jul. 4-7, 2018.
[57] Junil Lee, Ryoongbin Lee, Euyhwan Park, Sihyun Kim, Hyun-Min Kim, Kitae Lee, Soyoun Kim, Sangwan Kim , Jong-Ho Lee, and Byung-Gook Park, “Drive current boosting method of Fin-structure tunnel field-effect transistor with locally concentrated silicon-germanium channel,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, pp. 107-108, Jun. 17-18, 2018.
[56] Sangwan Kim , Peng Zheng, Kimihiko Kato, Leonard Rubin, and Tsu-Jae King Liu, “Cost-efficient sub-lithographic patterning with tilted-ion implantation (TII),” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, pp. 115-116, Apr. 16-19, 2018. [Invited]
[55] Sangwan Kim , Peng Zheng, Kimihiko Kato, Leonard Rubin, Seong-Su Shin, Hwa Young Gu, Shinhee Kim, and Tsu-Jae King Liu, “Device and process technologies for extending moore’s Law,” China Semiconductor Technology International Conference (CSTIC), Shanghai, China, Mar. 11-12, 2018. [Invited]
[54] Ryoongbin Lee, Suhyeon Kim, Sangwan Kim , Sihyun Kim, Junil Lee, Euyhwan Park, Hyun-Min Kim, Kitae Lee, and Byung-Gook Park, “Simulation study on influence of interface trap position in Si 1-x Ge x gate-all-around (GAA) field-effect transistor,” International Conference on Electronics, Information and Communication (ICEIC), Honolulu, HI, pp. 708-709, Jan. 24-27, 2018.
[53] Ava J. Tan, Justin C. Wong, Ajay K. Yadav, Korok Chatterjee, Daewoong Kwon, Sangwan Kim , Golnaz Karbasian, Sayeef Salahuddin, “Characterization of the interface trap density of ferroelectric hafnium zirconium oxide,” presented in Semiconductor Research Corporation (SRC) TECHCON , Austin, TX, USA, Sep. 10-12,2017. [Best in Session Award]
[52] Sangwan Kim , Peng Zheng, Kimihiko Kato, Leonard Rubin, and Tsu-Jae King Liu, “Sub-lithographic patterning by tilted ion implantation (TII),” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Gyeongju, Korea, pp. 71-72, Jul. 3-5, 2017. [Invited]
[51] Sangwook Kim, Dae Woong Kwon, and Sangwan Kim , “Temperature dependence of recessed-channel reconfigurable field-effect transistor (RC-RFET),” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Gyeongju, Korea, pp. 169-170, Jul. 3-5, 2017.
[50] Tsu-Jae King Liu, Peng Zheng, Sangwan Kim , Kimihiko Kato, and Vladimir Stojanovic, “There’s still plenty of room at the bottom – and at the top,” 75 th DeviceResearchConference(DRC), Notre Dame, IL, USA, Jun. 25-28, 2017. [Plenary]
[49] Golnaz Karbasian, Ava Tan, Ajay Yadav, Eric Martin Henry Sorensen, Claudy Rayan Serrao, Asif Islam Khan, Korok Chatterjee, Sangwan Kim , Chenming Hu, and Sayeef Salahuddin, “Ferroelectricity in HfO 2 thin films as a function of Zr doping,”International Symposiumon VLSI Technology, Systems and Applications(VLSI-TSA),Hsinchu,Taiwan,Apr.24-27,2017.
[48] Sang Wan Kim , Peng Zheng, Kimihiko Kato, Leonard Rubin, and Tsu-Jae King Liu, “Enhanced patterning by tilted ion implantation,” in SPIE 9777, Alternative Lithographic Technologies VIII , p. 97771B, Mar. 22, 2016. (presented at the SPIE Advanced Lithography Conference , San Jose, CA, USA, Feb. 21-25, 2016)
[47] Sang Wan Kim , Heesauk Jhon, and Woo Young Choi, “Miniature CMOS low noise amplifier in 0.18-um mixed-signal (Twin-Well) CMOS Process,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Seoul, Korea, pp. 40-43, Jun. 29-Jul. 2, 2015.
[46] Sang Wan Kim , Seongjae Cho, Byung-Gook Park, and Woo Young Choi, “Improvement of on-off current ratio in vertical electron-hole bilayer tunnel field-effect transistors (V-EHBTFETs),” International Conference on Electronics, Information and Communication (ICEIC), Singapore, pp. 376-377, Jan. 28-31, 2015.
[45] Junil Lee, Jang Hyun Kim, Hyun Woo Kim, Sang Wan Kim , Euyhwan Park, Myung Hyun Baek, and Byung-Gook Park, “Study on electrical characteristics of HfO2/Al2O3 bilayer MOS capacitor using atomic layer deposition,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 207-208, Jul. 2014.
[44] Hyun Woo Kim, Sang Wan Kim , Min-Chul Sun, Jang Hyun Kim, Euyhwan Park, and Byung-Gook Park, “Tunneling field-effect transistor with Si/SiGe material for high current drivability,” International Microprocesses and Nanotechnology Conference (MNC), Sapporo, Japan, p. 8P-11-37, Nov. 5-8, 2013.
[43] Byung-Gook Park, Min-Chul Sun, and Sang Wan Kim , “Silicon-based tunneling field effect transistors for ultra-low power applications,” Asia Pacific Physics Conference , Chiba, Japan, p. A2-2-I2, Jul. 14-19, 2013.
[42] Sang Wan Kim , Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Threshold voltage adjustment method of tunneling field-effect transistors,” International Conference on Electronics, Information and Communication (ICEIC), Bali, Indonesia, pp. 247-248, Jan. 30-Feb. 2, 2013.
[41] Hyun Woo Kim, Min-Chul Sun, Sang Wan Kim , and Byung-Gook Park, “Hump phenomenon in transfer characteristics of double-gated thin-body tunneling field-effect transistor (TFET) with Gate/Source overlap,” IEEE International NanoElectronics Conference (INEC), Singapore, pp. 386-388, Jan. 2-4, 2013.
[40] Min-Chul Sun, Hyun Woo Kim, Sang Wan Kim , Jung Han Lee, Hyungjin Kim, and Byung-Gook Park, “Threshold voltage of nanoscale Si gate-all-around MOSFET: short-channel, quantum, and volume effects,” IEEE International NanoElectronics Conference (INEC), Singapore, pp. 27-29, Jan. 2-4, 2013.
[39] Min-Chul Sun, Sang Wan Kim , Hyun Woo Kim, Hyungjin Kim, and Byung-Gook Park, “CMOS-compatible tunnel FETs with 14 nm gate, sigma-shape source, and recessed channel,” International Microprocesses and Nanotechnology Conference (MNC), Sapporo, Japan, pp. 1P-7-34-, Nov. 4-7, 2012.
[38] Hyun Woo Kim, Min-Chul Sun, Sang Wan Kim , Joo Yun Seo, Garam Kim, Jang Hyun Kim, and Byung-Gook Park, “Investigation on effects of changing body doping concentration in short-channel junctionless transistor,” International Microprocesses and Nanotechnology Conference (MNC), Sapporo, Japan, pp. 1P-7-41-, Nov. 4-7, 2012.
[37] Sang Wan Kim , Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Design improvement of L-shaped tunneling field-effect transistors,” IEEE International SOI Conference , Napa, CA, USA, pp. 4.1-, Oct. 1-4, 2012.
[36] Min-Chul Sun, Garam Kim, Jung Han Lee, Hyungjin Kim, Sang Wan Kim , Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Patterning of Si nanowire array with electron beam lithography for sub-22 nm Si nanoelectronics technology,” International Conference on Micro- and Nano-Engineering (MNE), Toulouse, France, pp. 281-282, Sep. 16-20, 2012.
[35] Sang Wan Kim , Woo Young Choi, Won Bo Shim, Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Study on the ambipolar behavior depending on the length of gate-drain overlap,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Sapporo, Japan, pp. P-T3-09-, Jul. 15-18, 2012.
[34] Sang Wan Kim , Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Investigation and optimization of the n-channel and p-channel L-shaped tunneling field-effect transistors,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Okinawa, Japan, pp. 36-37, Jun. 27-29, 2012.
[33] Min-Chul Sun, Sang Wan Kim , Garam Kim, Hyun Woo Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Novel tunneling field-effect transistor with sigma-shape embedded SiGe sources and recessed channel,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Okinawa, Japan, pp. 281-282, Jun. 27-29, 2012.
[32] Sang Wan Kim , Woo Young Choi, Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Investigation on hump effects of L-shaped tunneling field-effect transistors,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, pp. 169-170, Jun. 10-11, 2012.
[31] Sang Wan Kim , Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Ambipolar behavior of L-shaped tunneling field-effect transistors,” International Conference on Electronics, Information and Communication (ICEIC), Jeongseon, Korea, pp. 285-286, Feb. 1-3, 2012.
[30] Hyungjin Kim, Sang Wan Kim , Min-Chul Sun, Hyun Woo Kim, Garam Kim, Jang Hyun Kim, Euyhwan Park, and Byung-Gook Park, “Enhanced ambipolar characteristic of tunneling field-effect transistors using doped region,” International Conference on Electronics, Information and Communication (ICEIC), Jeongseon, Korea, pp. 279-280, Feb. 1-3, 2012.
[29] Min-Chul Sun, Sang Wan Kim , Garam Kim, Hyun Woo Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Modulation of transfer characteristics of Si nanowire tunnel FET on ultra-thin-body and BOX (UTBB) SOI substrate using back-gate bias,” International Semiconductor Device Research Symposium (ISDRS), College Park, MD, USA, pp. 1-2, Dec. 7-9, 2011.
[28] Garam Kim, Min-Chul Sun, Sang Wan Kim , Hyun Woo Kim, Jang Hyun Kim, Euyhwan Park, Hyungjin Kim, and Byung-Gook Park, “Novel MOSFET structure using p-n junction gate for ultra-low subthreshold-swing,” International Semiconductor Device Research Symposium (ISDRS), College Park, MD, USA, pp. 1-2, Dec. 7-9, 2011.
[27] Sang Wan Kim , Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “L-shaped tunneling field-effect transistors (TFETs) for low subthreshold swing and high current drivability,” International Microprocesses and Nanotechnology Conference (MNC), Kyoto, Japan, pp. 26C-4-5L-26C-4-5L, Oct. 24-27, 2011.
[26] Min-Chul Sun, Sang Wan Kim , Hyun Woo Kim, Garam Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Design of thin-body double-gated vertical-channel tunneling field-effect transistors for ultra-low power logic circuits,” International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, pp. 845-846, Sep. 28-30, 2011.
[25] Garam Kim, Sang Wan Kim , Min-Chul Sun, Hyun Woo Kim, Hyungjin Kim, and Byung-Gook Park, “Tunneling field effect transistor with sidewall floating gate for ultra-low subthreshold swing,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Gyeongju, Korea, pp. 306-307, Jun. 19-22, 2011.
[24] Min-Chul Sun, Hyun Woo Kim, Sang Wan Kim , Garam Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Comparative study on top- and bottom-source vertical-channel tunnel field-effect transistors,” Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices (AWAD), Daejeon, Korea, pp. 87-89, Jun. 29-Jul. 1, 2011.
[23] Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, Sang Wan Kim , Garam Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Threshold voltage control of tunnel field-effect transistors using V T -control doping region,” Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices (AWAD), Daejeon, Korea, pp. 90-92, Jun. 29-Jul. 1, 2011.
[22] Min-Chul Sun, Sang Wan Kim , Garam Kim, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Scalable embedded Ge-junction vertical-channel tunneling field-effect transistor for low-voltage operation,” IEEE Nanotechnology Materials and Devices Conference (NMDC), Monterey, CA, USA, pp. 286-290, Oct. 12-15, 2010.
[21] Jisoo Chang, Sang Wan Kim , Dae Woong Kwon, Jang Hyun Kim, Jae Chul Park, Ihun Song, U-In Jung, Chang Jung Kim, and Byung-Gook Park, “Investigation of bias temperature instability in HfInZnO thin film transistor,” International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, pp. 379-380, Sep. 22-24, 2010.
[20] Min-Chul Sun, Wandong Kim, Jeong-Hoon Oh, Kyung-Chang Ryoo, Sang Wan Kim , Garam Kim, Hyun Woo Kim, Sunghun Jung, Dae Woong Kwon, Jisoo Chang, Jang Hyun Kim, and Byung-Gook Park, “Influence of sidewall thickness variation on transfer characteristics of L-shaped impact-ionization MOS transistor,” IEEE NANO , Seoul, Korea, pp. 250-253, Aug. 17-20, 2010.
[19] Sang Wan Kim , Garam Kim, Won Bo Shim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Simulation of retention characteristics in a double-gate and recessed-channel 1T DRAM cell with high reliability,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Pattaya, Thailand, pp. 905-906, Jul. 4-7, 2010.
[18] Jang-Gn Yun, Dae Woong Kwon, Sang Wan Kim , Jong-Ho Lee, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, “Dumbbell-shaped nanowire with body contact region for three dimensional (3D) NAND flash memory application,” International Conference on Electronics, Information and Communication (ICEIC), Cebu, Philippines, pp. 5-7, Jun. 30-Jul. 2, 2010.
[17] Kyung-Chang Ryoo, Jeong-Hoon Oh, Sunghun Jung, Sang Wan Kim , Min-Chul Sun, Garam Kim, Hyun Woo Kim, Dae Woong Kwon, Jisoo Chang, Jang Hyun Kim, Hongsik Jeong, and Byung-Gook Park, “Relationships of resistive switching parameters of resistive random access memory (RRAM) for high density and low power application,” International Conference on Electronics, Information and Communication (ICEIC), Cebu, Philippines, pp. 11-13, Jun. 30-Jul. 2, 2010.
[16] Sang Wan Kim , Garam Kim, Wonjoo Kim, Hyoungsoo Ko, and Byung-Gook Park, “Investigation of 1T DRAM cell with non-overlap structure and recessed channel,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, pp. 139-140, Jun. 13-14, 2010.
[15] Jae Young Song, Jong Pil Kim, Sang Wan Kim , Jeong-Hoon Oh, Kyung-Chang Ryoo, Min-Chul Sun, Garam Kim, Hyun Woo Kim, Jisoo Chang, Sunghun Jung, Hyungcheol Shin, and Byung-Gook Park, “Fabrication and characterization of buried-gate fin and recess channel MOSFET for high performance and low GIDL current,” International Semiconductor Device Research Symposium (ISDRS), College Park, MD, USA, Dec. 9-11, 2009.
[14] Seongjae Cho, Sang Wan Kim , Kazuhiko Endo, Shinichi O'uchi, Takashi Matsukawa, Younghwan Son, Jong Pil Kim, Kunihiro Sakamoto, Yongxun Liu, Byung-Gook Park and Meishoku Masahara, “Rigorous design of 20 nm level SOI 4-T FinFETs for low standby power by extracting parameters from the pre-stage 50 nm technology node devices,” Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, pp. 380-381, Oct. 7-9, 2009.
[13] Jae Hyun Park, Jae Young Song, Jong Pil Kim, Sang Wan Kim , Jeong-Hoon Oh, Kyung-Chang Ryoo, Garam Kim, Hyun Woo Kim, and Byung-Gook Park, “Fabrication and analysis of the gate-all-around (GAA) structure silicon nanowire MOSFET,” IEEE Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, pp. 13-14, Jun. 13-14, 2009.
[12] Jae Young Song, Jong Pil Kim, Sang Wan Kim , Jeong-Hoon Oh, Kyung-Chang Ryoo, Jae Hyun Park, Garam Kim, Hyun Woo Kim, Atteq Ur Rehman, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, “Buried-gate fin and recess channel MOSFET for sub-30 nm DRAM cell transistors with high performance and low GIDL current,” IEEE Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, pp. 51-52, Jun. 13-14, 2009.
[11] Garam Kim, Sang Wan Kim , Jae Young Song, Jong Pil Kim, Kyung-Chang Ryoo, Jeong-Hoon Oh, Jae Hyun Park, Hyun Woo Kim and Byung-Gook Park, “Body-raised double-gate structure for 1T DRAM,” IEEE Nanotechnology Materials and Devices Conference (NMDC), Traverse City, MI, USA, pp.259-263, Jun. 2-5, 2009.
[10] Jae Young Song, Jong Pil Kim, Sang Wan Kim , Jae Hyun Park, Garam Kim, Jong Duk Lee and Byung-Gook Park, “Design consideration for source/drain and LDD junction of FiReFET,” IEEE Nanotechnology Materials and Devices Conference (NMDC), Kyoto, Japan, pp.150, Oct. 20-22, 2008.
[09] Jong Pil Kim, Jae Young Song, Sang Wan Kim , Han Ki Chung, Jae Hyun Park, Hee Sauk Jhon, Garam Kim, Hyungcheol Shin, Jong Duk Lee and Byung-Gook Park, “High performance RF characteristics of asymmetric MOSFETs,” IEEE Nanotechnology Materials and Devices Conference (NMDC), Kyoto, Japan, p.56, Oct. 20-22, 2008.
[08] Han Ki Chung, Hoon Jeong, Yeun Seung Lee, Jae Young Song, Jong Pil Kim, Sang Wan Kim , Jae Hyun Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, “A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, M0345, Jun. 15-16, 2008.
[07] Sang Wan Kim , Jae Young Song, Jong Pil Kim, Woo Young Choi, Han Ki Chung, Jae Hyun Park, Hyoungsoo Ko, Seungbum Hong, Hongsik Park, Chulmin Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, “Investigation of resistive probes with high sensitivity,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, P2-15, Jun. 15-16, 2008.
[06] Jae Young Song, Jong Pil Kim, Sang Wan Kim , Han Ki Jung, Jae Hyun Park, Jong Duk Lee, and Byung-Gook Park, “Fin and recess channel MOSFET (FiReFET) for performance enhancement of sub-50 nm DRAM cell,” International Semiconductor Device Research Symposium (ISDRS), College Park, MD, USA, Dec. 12-14, 2007.
[05] Jong Pil Kim, Jae Young Song, Sang Wan Kim , Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, “30-nm asymmetric NMOSFET using a novel fabrication method,” IEEE Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, pp. 89-90, Jun. 10-11, 2007.
[04] Sang Wan Kim , Woo Young Choi, Jae Young Song, Jong Pil Kim, Junsoo Kim, Hyoungsoo Ko, Hongsik Park, Chulmin Park, Seungbum Hong, Sung-Hoon Choa, Jong Duk Lee, Hyungcheol Shin and Byung-Gook Park, “Analysis and modeling of resistive probes,” IEEE Nanotechnology Materials and Devices Conference (NMDC), Gyeongju, Korea, pp. 318-319, Oct. 22-25, 2006.
[03] Woo Young Choi, Jae Young Song, Jong Pil Kim, Sang Wan Kim , Jong Duk Lee, and Byung-Gook Park, “Breakdown voltage reduction in I-MOS devices,” IEEE Nanotechnology Materials and Devices Conference (NMDC), Gyeongju, Korea, pp. 380-381, Oct. 22-25, 2006.
[02] Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sangwoo Kang, Sang Wan Kim , Jong Duk Lee, and Byung-Gook Park, “Design and simulation of asymmetric MOSFETs,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Sendai, Japan, pp. 175-178, Jul. 3-5, 2006.
[01] Jae Young Song, Woo Young Choi, Jong Pil Kim, Sang Wan Kim , Doo-Hyun Kim, Jin Ho Kim, Dong-Wook Park, Jong Duk Lee, and Byung-Gook Park, “Effects on multi-fin on self-aligned gate-all-around MOSFETs,” International Conference on Electronics, Information and Communication (ICEIC), Ulaanbaatar, Mongolia, pp. 21-24, Jun. 27-28, 2006.
Domestic Conference
[99] Yuhyun Park, Suhong Min, Ho Jun Kim, Jinhwan Jung, Seonggeun Kim and Sangwan Kim, “Study about buried gate DRAM cell transistor with variation of dual work-function gate,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. , Feb. 12-14, 2025.
[98] Changmin Kang, Wonyong Oh, Sunwoo Lee, Seungwon Go and Sangwan Kim, “Simulation study of heterojunction ferroelectric tunnel field effect transistor,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. , Feb. 12-14, 2025.
[97] Sang Eun Jee, Jaewon Jang, Youn Seok Kye and Sangwan Kim, “Effects of gate/drain bias on electrical performance degradation in a-IGZO TFT,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. , Feb. 12-14, 2025.
[96] Yoonsoo Choi, Chanhyeok Park, Hyungju Noh, Yelim Jeon and Sangwan Kim, “Analysis of memory characteristics of gate-injection ferroelectric field-effect transistor (GI-FeFET) with different gate stack thicknesses,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. , Feb. 12-14, 2025.
[95] Gwanguk Woo, Harin Lee, Dong Keun Lee, Taegun Kim and Sangwan Kim, “Simulation of self-heating effects in vertically-stacked nanosheet FET,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. , Feb. 12-14, 2025.
[94] Jiwoong Choi, Dong Keun Lee, Taegun Kim and Sangwan Kim, “Optimization of ternary logic inverter circuit based on dual-channel metal-oxide-semiconductor field-effect transistor,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. , Feb. 12-14, 2025.
[93] Seungyeon Park, Seonggeun Kim, Jinhwan Jung and Sangwan Kim, “Study about memory characteristics in hemi-cylindrical ferroelectric vertical NAND (HC Fe-VNAND),” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. , Feb. 12-14, 2025.
[92] Jaewon Jang, Youn Seok Kye, Sangwan Kim, “The impacts of annealing ambient on stability for a-IGZO TFT,” Autumn Annual Conference of IEIE, Jeongseon, Korea, p. 477-478, Nov. 22-23, 2024.
[91] Jaekyun Son, Jae Yeon Park, Sangwan Kim, “Investigation of reconfigurable field-effect transistor (FBFET) with body thickness variation,” Autumn Annual Conference of IEIE, Jeongseon, Korea, p. 479-481, Nov. 22-23, 2024.
[90] Jinhwan Jung, Seonggeun Kim, Seungwon Go, and Sangwan Kim, “Simulation study on memory characteristics of recessed double gate ferroelectric-metal field-effect-transistors,” Summer Annual Conference of IEIE, Jeju, Korea, p. 722-724, Jun. 26-28, 2024.
[89] Youn Seok Kye, Jae Yeon Park, and Sangwan Kim, “Investigation of complementary tunnel FET (CTFET) for low-power operation,” Summer Annual Conference of IEIE, Jeju, Korea, p. 826-829, Jun. 26-28, 2024.
[88] Youn Seok Kye, Jae Yeon Park, and Sangwan Kim, “Analysis of hot carrier injection (HCI) and Fowler-Norheim (FN) tunneling mechanisms in charge trap flash (CTF) memory Device,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 948, Jan. 24-26, 2024.
[87] Chang Min Chae, Hyung Ju Noh, and Sangwan Kim, “Optimization of measurement error in cross bridge Kelvin resistor based on Ti silicide,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 916, Jan. 24-26, 2024.
[86] Sanghyeok Seo, Seongju Cho, Hansoo Chae, Yelim Jeon, and Sangwan Kim, “Comparison of optimized tunneling oxide thickness between floating gate flash and charge trap flash,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 873, Jan. 24-26, 2024.
[85] Un-hyun Im, Dogyun Ahn, Tae-young Yun, Jang Hyun Kim, and Sangwan Kim, “Investigation of self-heating effects in SOI L-shaped MOSFET with various position of the Al2O3 heat sink using 3-D TCAD simulation,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 612, Jan. 24-26, 2024.
[84] Hyungju Noh, Yelim Jeon, Sihyun Kim, and Sangwan Kim, “A novel hybrid ferroelectric charge trap layer gate-injection flash,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 608, Jan. 24-26, 2024.
[83] Jinhong Lee, Jae Yeon Park, Jaekyun Son, Tae-Hyeon Kim, Sihyun Kim, and Sangwan Kim, “Analysis of memory characteristics in charge trap flash devices depending on tunnel oxide,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 604, Jan. 24-26, 2024.
[82] Jaekyun Son, Jae Yeon Park, Tae-Hyeon Kim, Sihyun Kim, and Sangwan Kim, “Effects of tunnel oxide on reliability in charge trap flash memory devices,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 603, Jan. 24-26, 2024.
[81] Yelim Jeon, Hyungju Noh, Tae-Hyeon Kim, Sihyun Kim, and Sangwan Kim, “Simulation studies of gate-injection ferroelectric flash (GI FeFlash),” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 595, Jan. 24-26, 2024.
[80] Heebum Kang, Seungmin Kang, Tae-Hyeon Kim, Sangwan Kim, and Sihyun Kim, “Multi-bit vertical ferroelectric-metal field-effect transistor (V-FeMFET) weight cell for neuromorphic computing,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 592, Jan. 24-26, 2024.
[79] Taegun Kim, Dong Keun Lee, Sihyun Kim, and Sangwan Kim, “A simulation study of heterojunction FeFET with SiGe body for efficient erase operation,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 591, Jan. 24-26, 2024.
[78] Yun Seo Choi, Seungwon Go, Tae-Hyeon Kim, Sihyun Kim, and Sangwan Kim, “Analysis on the impact of charge traps in FeTFET,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 590, Jan. 24-26, 2024.
[77] Chankoo Kim, Dong Keun Lee, Seonggeun Kim, Tae-Hyeon Kim, Sihyun Kim, and Sangwan Kim, “Analysis of interface trap density in metal-ferroelectric-insulator-semiconductor (MFIS) capacitor with high-k dielectrics,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 588, Jan. 24-26, 2024.
[76] Jinhwan Jung, Seonggeun Kim, and Sangwan Kim, “Investigation of oxygen-scavenging effect on Hf0.5Zr0.5O2 metal-ferroelectric-insulator semiconductor (MFIS) stack with CMOS compatible gate structure,” Korean Conference on Semiconductors (KCS), Gyeongju, Korea, p. 583, Jan. 24-26, 2024.
[75] Jaewon Jang, Hyungju Noh, and Sangwan Kim, “Development of self-aligned Silicide process for MOS capacitor,” The institute of Semiconductor Engineers (ISE) Integrated Academic Conference, Seoul, Korea, PS-6, Dec. 1, 2023.
[74] Hyungju Noh, Jaewon Jang, and Sangwan Kim, “Design and measurement of cross bridge kelvin resistor (CBKR) for minimizing contact resistance errors,” The institute of Semiconductor Engineers (ISE) Integrated Academic Conference, Seoul, Korea, PS-5, Dec. 1, 2023.
[73] Namsung Kim, Sangwan Kim, Wooyoung Jung, Hunguen Lee, Youngsoo Han, Changsup Kim, Younggin Lee, Jaeyoung Suk, Hyungju Noh, and Jaewon Jang, “Analysis of flat-top nanosecond green laser annealing process of silicon semiconductor wafers,” The Institute of Semiconductor Engineers (ISE) Summer Conference, Gyeongju, Korea, PS-2, Jul. 17, 2023.
[72] Hyunho Ahn, Seungwon Go, Dong Keun Lee, Jang Hyun Kim and Sangwan Kim, “Optimization of double-gate TFET with vertical channel sandwitched by lightly doped Si,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 808, Feb. 13-15, 2023.
[71] Seonggeun Kim, Hyungju Noh, Seungwon Go and Sangwan Kim, “Improvement of on/off current ratio (Ion/Ioff) in hafnium-based ferroelectric tunnel junction (FTJ),” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 134, Feb. 13-15, 2023.
[70] Shinhee Kim, Dong Keun Lee, Jae Yeon Park and Sangwan Kim, “Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND/NOR array operation,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 130, Feb. 13-15, 2023.
[69] Dong Keun Lee and Sangwan Kim, “Analysis of polarization gradient effect on negative capacitance tunnel field-effect transistor (NC-TFET),” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 742, Jan. 24-26, 2022.
[68] Unhyun Im and Sangwan Kim, “Approach for Ge-rich SiGe growth using Ge deposited by PVD method,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 185, Jan. 24-26, 2022.
[67] Jae Yeon Park, Seungwon Go, Shinhee Kim, and Sangwan Kim, “Design optimization of negative capacitance field-effect transistor (NCFET) with hetero-metal gate to suppress the reverse drain-induced barrier lowering,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 58, Jan. 24-26, 2022.
[66] Sora Park and Sangwan Kim, “Study about the effects of interface trap level on bias temperature instability (BTI) in gate-all-around field-effect transistor (GAA FET)”, NANO Korea, Goyang-si, Korea, p.798, Jul. 7-9, 2021.
[65] Jae Yeon Park and Sangwan Kim , “A novel recessed-channel field-effect transistor with T-shaped gate,” NANO Korea, Goyang-si, Korea, p. 793, Jul. 7-9, 2021.
[64] Seungwon Go and Sangwan Kim , “Impact of drain mole fraction on capacitor-less one-transistor (1T) dynamic random access memory (DRAM),” NANO Korea, Goyang-si, Korea, 792, Jul. 7-9, 2021.
[63] Dongkeun Lee, Ryoongbin Lee, Kitae Lee, Sihyun Kim, Byung-Gook Park and Sangwan Kim, “Impact of channel width on electrical characteristics of I-shaped and fin tunnel field-effect transistor (TFET),” NANO Korea, Goyang-si, Korea, p. 791, Jul. 7-9, 2021.
[62] Shinhee Kim and Sangwan Kim , “Suppression of negative differential resistance (NDR) in negative capacitance tunnel field-effect transistor (NC-TFET) with gate-drain underlap structure,” NANO Korea, Goyang-si, Korea, p. 790, Jul. 7-9, 2021.
[61] Joonho Park, Unhyun Im, and Sangwan Kim , “Study on the I/V characteristic of MOSFET with VO2 as a gate dielectric,” Korean Conference on Semiconductors (KCS), Online, Korea, p. 461, Jan. 25-29, 2021.
[60] Mun-Jeong Choe and Sangwan Kim , “Improvement of electrical characteristics of heterojunction fin tunnel field-effect transistor (Fin TFET) with negative capacitance,” Korean Conference on Semiconductors (KCS), Online, Korea, p. 460, Jan. 25-29, 2021.
[59] Sora Park and Sangwan Kim , “Optimization of intrinsic layer for high on-state current in multi-bridge-channel tunnel field-effect transistor (MBC TFET),” Korean Conference on Semiconductors (KCS), Online, Korea, p. 451, Jan. 25-29, 2021.
[58] Seungwon Go and Sangwan Kim , “Impact of spacer materials and gate underlap on double gate negative capacitance tunnel field-effect transistor (DGNC-TFET),” Korean Conference on Semiconductors (KCS), Online, Korea, p. 208, Jan. 25-29, 2021.
[57] Jae Yeon Park and Sangwan Kim , “Optimization of sidewall spacer to enhance negative capacitance field-effect transistor (NCFET) electrical characteristics,” Korean Conference on Semiconductors (KCS), Online, Korea, p. 207, Jan. 25-29, 2021.
[56] Shinhee Kim and Sangwan Kim , “Investigation on negative differential resistance (NDR) of negative capacitance tunnel field-effect transistor (NC-TFET)," Korean Conference on Semiconductors (KCS), Online, Korea, p. 206, Jan. 25-29, 2021.
[55] Mun-Jeong Choe and Sangwan Kim , “Impact of fin height on the on-current characteristic of bulk FinFET with top source/drain contacts,” IEIE Fall Conference , Gwangju, Korea, pp. 202-203, Nov. 27-28, 2020.
[54] Sora Park and Sangwan Kim , “Effects of extended gate structure on electrical characteristics of junctionless tunnel field-effect transistor,” IEIE Fall Conference , Gwangju, Korea, pp. 41-42, Nov. 27-28, 2020. [Best Paper Award]
[53] Shinhee Kim, Jae Yeon Park, Hyug Su Kwon, Woo Young Choi, and Sangwan Kim , “Low-power nanoelectromechanical (NEM) device with HfO2-based ferroelectric capacitor,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 624, Feb. 12-14, 2020.
[52] Un-Hyun Im, Seok Jung Kang, and Sangwan Kim , “A novel strategy for Ge-rich Si 1-x Ge x layer,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 248, Feb. 12-14, 2020.
[51] SeokJung Kang, Seong Soo Shin, and Sangwan Kim , “Influence of Ar plasma treatment on metal-insulator-semiconductor (MIS) contact resistivity,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 247, Feb. 12-14, 2020.
[50] Jae Yeon Park, Hyun-Ho Ahn, Seungwon Go, and Sangwan Kim , “Analysis of parasitic capacitance effect on nanowire negative capacitance field-effect transistor (NW-NCFET),” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 243, Feb. 12-14, 2020.
[49] Changha Kim, Kitae Lee, Junil Lee, Ryoongbin Lee, Sihyun Kim, Hyun-min Kim, Sangwan Kim and Byung-Gook Park, “Switching characteristics analysis of tunnel field-effect transistor with elevated drain by changing drain underlap length,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 18, Feb. 12-14, 2020.
[48] Garam Kim, and Sangwan Kim , “Optimization of spacer and source/channel junction to improve TFET characteristics,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 17, Feb. 12-14, 2020.
[47] Shinhee Kim, Hyun Ho Ahn, and Sangwan Kim , “Study about the influence of temperature on phase transition of HfZrO,” IEEK Summer Conference, Jeju, Korea, p. 329, Jun. 26-28, 2019.
[46] KyungJin Rim and Sangwan Kim , “Theoretical study for the hysteresis-free operation of negative capacitance field-effect transistor (NCFET),” IEEK Summer Conference, Jeju, Korea, p. 151, Jun. 26-28, 2019.
[45] Kitae Lee, Sihyun Kim, Munhyeon Kim, Sangwan Kim , and Byung-Gook Park, “Analysis on capacitance characteristics in FE-GAA MOSFET,” IEEK Summer Conference, Jeju, Korea, p. 137, Jun. 26-28, 2019.
[44] Sihyun Kim, Junil Lee, Junsu Yu, Kitae Lee, Munhyeon Kim, Sangwan Kim , and Byung-Gook Park, “Suppression of ambipolar current using sidewall spacer in L-shaped tunnel field-effect transistor,” IEEK Summer Conference, Jeju, Korea, p. 106, Jun. 26-28, 2019.
[43] Ryoongbin Lee, Junil Lee, Kitae Lee, Soyoun Kim, Sihyun Kim, Sangwan Kim , and Byung-Gook Park, “Proposal of I-shaped SiGe fin tunnel field-effect transistor (TFET),” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 670, Feb. 13-15, 2019.
[42] Tae chan Kim, Shinhee Kim, Jang Hyun Kim, and Sangwan Kim , “Comparison of work function variation between fin and nanowire tunnel field-effect transistors (TFETs),” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 658, Feb. 13-15, 2019.
[41] Jinuk Hwang, Hwa Young Gu, Jang Hyun Kim, and Sangwan Kim , “Random dopant fluctuation (RDF) effects in nanowire tunnel field-effect transistors (TFETs),” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 657, Feb. 13-15, 2019.
[40] Min Gyu Lee, Seong-Su Shin, Jang Hyun Kim, and Sangwan Kim , “Investigation on line-edge roughness (LER) effects between nanowire tunnel FETs (TFETs) and MOSFETs,” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 656, Feb. 13-15, 2019.
[39] Jeong-Uk Park, KyungJin Rim, Jang Hyun Kim, and Sangwan Kim , “Improvement of reliability and performance in stacked nanowire tunnel field-effect transistor (TFET) using silicon germanium,” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 655, Feb. 13-15, 2019.
[38] Seong-Hyun Lee, Ye Sung Kwon, Jang Hyun Kim, and Sangwan Kim , “Surrounding channel nanowire tunnel field-effect transistor (SCNW-TFET) with dual-gate to reduce a hump phenomenon,” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 286, Feb. 13-15, 2019.
[37] Junil Lee, Ryoongbin Lee, Sihyun Kim, Hyun-Min Kim, Kitae Lee, Soyoun Kim, Munhyeon Kim, Yunho Choi, Sangwan Kim, and Byung-Gook Park, “Demonstration of Ge condensed SiGe channel tunnel FETs and co-integration with CMOS,” Korean Confere nce on Semiconductors (KCS), Dunnae, Korea, p. 283, Feb. 13-15, 2019.
[36] Yunho Choi, Kitae Lee, Kyoung Yeon Kim, Sihyun Kim, Junil Lee, Ryoongbin Lee, Hyun-Min Kim, Young Suh Song, Sangwan Kim , and Byung-Gook Park, “Simulation study on the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET,” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 82, Feb. 13-15, 2019.
[35] Munhyeon Kim, Sihyun Kim, Kitae Lee, Soyoun Kim, Junil Lee, Hyun-Min Kim, Ryoongbin Lee, Sangwan Kim , and Byung-Gook Park, “Effective work function modulation using dipole mechanism with Al2O3 on HfO2 atomic layer deposition,” Korean Conference on Semiconductors (KCS), Dunnae, Korea, p. 16, Feb. 13-15, 2019.
[34] Ryoongbin Lee, Sangwan Kim , Kitae Lee, Sihyun Kim, Dae Woong Kwon, and Byung-Gook Park, “Nonvolatile memory (NVM) operation of tunnel field-effect transistor (TFETs) using doped-HfO 2 sidewall,” NANO Korea , Goyang-si, Korea, p. O1801_0060, Jul. 11-13, 2018.
[33] Jang Hyun Kim, Seong-Su Shin, and Sangwan Kim , “Transient analysis of tunnel field-effect transistor with raised drain,” NANO Korea , Goyang-si, Korea, p. P1801_0365, Jul. 11-13, 2018.
[32] Munhyeon Kim, Kitae Lee, Sihyun Kim, Sangwan Kim , and Byung-Gook Park, “A novel PMOS stacked nanosheet gate-all-around field-effect transistor PMOS structure for device optimization,” IEEK Summer Conference , Jeju, Korea, pp. 233-235, Jun. 27-2 9, 2018.
[31] Kitae Lee, Junil Lee, Sihyun Kim, Munhyeon Kim, Sangwan Kim, and Byung-Gook Park, “Analysis of silicon etching characteristic by channel direction using TMAH,” IEEK Summer Conference , Jeju, Korea, pp. 140-142, Jun. 27-29, 2018.
[30] Sihyun Kim, Suhyeon Kim, Hyungwoo Ko, Sangwan Kim, and Byung-Gook Park, “Simulation study on the effect of gate-to-source/drain overlap length on the extension resistance of gate-all-around field effect transistors,” IEEK Summer Conference , Jeju, K orea, pp. 63-65, Jun. 27-29, 2018.
[29] Sangwan Kim , “Ultra-low power device technologies for energy efficient computing system,” IEEK Summer Conference , Jeju, Korea, Jun. 27-29, 2018. [Invited]
[28] Kitae Lee, Junil Lee, Ryoongbin Lee, Euyhwan Park, Sihyun Kim, Hyun-Min Kim, Sangwan Kim , and Byung-Gook Park, “Tunnel field effect transistor with ferroelectric gate dielectric,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 57 1, Feb. 5-7, 2018.
[27] Sihyun Kim, Suhyun Kim, Sangwan Kim , Euyhwan Park, Junil Lee, Ryoongbin Lee, Soyeon Kim, Hyun-Min Kim, Kitae Lee, Jong-Ho Lee, and Byung-Gook Park, “Simulation study on the effect of unconformal work-function metal deposition on the electrical characteristic of stacked-GAA MOSFET,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 519, Feb. 5-7, 2018.
[26] Seong-Hyun Lee, Jeong-Uk Park, and Sangwan Kim , “Nanowire tunnel field-effect transistor (TFET) with ultra-thin-tunnel region for high current drivability and low subthreshold swing,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 4 04, Feb. 5-7, 2018.
[25] Junil Lee, Ryoongbin Lee, Euyhwan Park, Sihyun Kim, Hyun-Min Kim, Kitae Lee, Soyoun Kim, Sangwan Kim , and Byung-Gook Park, “Drive current boosting method of tunnel FET with locally concentrated silicon-germanium channel near surface,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 402, Feb. 5-7, 2018.
[24] Hwa Young Gu and Sangwan Kim , “Double-gate isosceles trapezoid tunnel field-effect transistor (DGIT-TFET) to suppress ambipolar current,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 400, Feb. 5-7, 2018.
[23] Sangwan Kim , Seong-Su Shin, Hwa Young Gu, and Shinhee Kim, “Highly CMOS compatible strategies for extending moore’s Law,” Korean Conference on Semiconductors (KCS), Jeongseon, Korea, p. 91, Feb. 5-7, 2018. [Invited]
[22] Sang Wan Kim and Woo Young Choi, “Enhanced compact model for Ge-Si heterojunction double-gate tunnel field-effect transistors (TFET),” NANO Korea , Goyang-si, Korea, p. P1701_0654, Jul. 12-14, 2017.
[21] Sang Wan Kim , Woo Young Choi, Jang Hyun Kim, Hyun Woo Kim, Euyhwan Park, Junil Lee, Taehyung Park, and Byung-Gook Park, “Vertical structured electron-hole bilayer tunnel field-effect transistors (V-EHBTFETs) for complementary logic applications,” NANO Korea , Seoul, Korea, p. P1401_079, Jul. 1-3, 2014.
[20] Sang Wan Kim , Woo Young Choi, Hyun Woo Kim, Jang Hyun Kim, Euyhwan Park, Junil Lee, Taehyung Park, and Byung-Gook Park, “Investigation on transient response in tunnel field-effect transistors (TFETs) depending on device geometric parameters,” NANO Korea , Seoul, Korea, p. P1401_080, Jul. 1-3, 2014.
[19] Hyun Woo Kim, Jong Pil Kim, Sang Wan Kim , Min-Chul Sun, Garam Kim, Jang Hyun Kim, Euyhwan Park, and Byung-Gook Park, “Schottky barrier tunneling field-effect transistor using spacer technique,” Korean Conference on Semiconductors (KCS), Seoul, Korea, pp. 294-294, Feb. 24-26, 2014.
[18] Sang Wan Kim , Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, “Study on the corner effect of L-shaped tunneling field-effect transistors,” NANO Korea , Seoul, Korea, p. O1201_010, Aug. 16-18, 2012.
[17] Euyhwan Park, Garam Kim, Jang Hyun Kim, Sang Wan Kim , Joong-Kon Son, Donghoon Kang, and Byung-Gook Park, “Analysis of cathodoluminescence image using ITO wet-etch process in GaN-based light-emitting diodes (LEDs),” IEEK Summer Conference, Jeju, Korea, pp. 77-78, Jun. 27-29, 2012.
[16] Sang Wan Kim , Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Investigation on the effects of tunneling barrier width on tunneling field effect transistors (TFETs) performance,” IEEK Summer Conference , Jeju, Korea, pp. 138-141, Jun. 27-29, 2012.
[15] Min-Chul Sun, Hyungjin Kim, Sang Wan Kim , Garam Kim, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Ground-plane doping for V T -modulation of planar tunnel field-effect transistors on ultra-thin-body and BOX (UTBB) SOI substrate,” Korean Conference on Semiconductors (KCS), Seoul, Korea, pp. 123-124, Feb. 15-17, 2012.
[14] Hyun Woo Kim, Hyungjin Kim, Sang Wan Kim , Min-Chul Sun, Garam Kim, Euyhwan Park, Jang Hyun Kim, and Byung-Gook Park, “A novel fabrication method for nanoscale tunneling field-effect transistor,” NANO Korea , Seoul, Korea, p. O1102_006, Aug. 24-26, 2011.
[13] Min-Chul Sun, Garam Kim, Sang Wan Kim , Hyun Woo Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Co-integration of nano-scale vertical- and horizontal-channel MOSFETs for low power CMOS technology,” NANO Korea , Seoul, Korea, p. O1101_010, Aug. 24-26, 2011.
[12] Garam Kim, Jang Hyun Kim, Euyhwan Park, Joong-Kon Son, Daeyoung Woo, Sang Wan Kim , Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Optical and electrical degradation of GaN LED by thermal stress,” NANO Korea , Seoul, Korea, p. P1101_178, Aug. 24-26, 2011.
[11] Euyhwan Park, Garam Kim, Jang Hyun Kim, Sang Wan Kim , Joong-Kon Son, Daeyoung Woo, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Analysis of current saturation delay in GaN-based light-emitting diodes (LEDs),” IEEK Summer Conference, Jeju, Korea, pp. 461-462, Jun. 22-24, 2011.
[10] Hyun Woo Kim, Sang Wan Kim , Min-Chul Sun, Garam Kim, Dae Woong Kwon, Jisoo Chang, Jang Hyun Kim, Euyhwan Park, and Byung-Gook Park, “Fabrication method to reduce ambipolar effects in tunneling field-effect transistors,” IEEK Fall Conference, Seoul, Korea, pp. 46-47, Nov. 23, 2010.
[09] Garam Kim, Sang Wan Kim , Kyung-Chang Ryoo, Jeong-Hoon Oh, Min-Chul Sun, Hyun Woo Kim, Dae Woong Kwon, Jisoo Chang, Sunghun Jung, Jang Hyun Kim, and Byung-Gook Park, “Split gate structure 1T DRAM for improving retention characteristics,” NANO Korea , Goyang, Korea, p. 1034, Aug. 17-20, 2010.
[08] Sang Wan Kim , Garam Kim, Won Bo Shim, Min-Chul Sun, Hyun Woo Kim, Dae Woong Kwon, Jisoo Chang, Jang Hyun Kim, Euyhwan Park, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “1T DRAM cell with twin gates and recessed channel,” IEEK Summer Conference , Jeju, Korea, pp. 723-724, Jun. 16-18, 2010.
[07] Min-Chul Sun, Sang Wan Kim , Garam Kim, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Short-channel characteristics of tunneling field-effect transistor and operation of vertical-channel tunneling field-effect transistor,” IEEK Summer Conference , Jeju, Korea, pp. 727-729, Jun. 16-18, 2010.
[06] Seongjae Cho, Sang Wan Kim , Younghwan Son, Il Han Lark, Jong Pil Kim, Hyungcheol Shin, and Byung-Gook Park, “The extraction of effective junction area and carrier lifetimes of PN-junctions with unknown geometry from capacitance measurements,” IEEK Summer Conference , Korea, pp. 399-400, Jul. 8-10, 2009.
[05] Garam Kim, Sang Wan Kim , Jae Young Song, Jong Pil Kim, Jeong-Hoon Oh, Kyung-Chang Ryoo, Hyun Woo Kim, Atteq-ur-Rehman, and Byung-Gook Park, “Optimization of block refresh (autonomous refresh) method for 1T DRAM,” IEEK Summer Conference, Jeju, Korea, pp. 385-386, Jul. 8-10, 2009.
[04] Jae Young Song, Jong Pil Kim, Sang Wan Kim , Han Ki Jung, Jae Hyun Park, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, “Fin and recess channel MOSFET (FiReFET) for high performance DRAM cell,” Korean Conference on Semiconductors (KCS), Pyeongchang, Korea, pp. 427-428, Feb. 20-22, 2008.
[03] Jong Pil Kim, Jae Young Song, Sang Wan Kim , Han Ki Jung, Jae Hyun Park, Hee Sauk Jhon, Yeonam Yoon, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park “RF performance of 50-nm self-aligned asymmetric MOSFET,” Korean Conference on Se miconductors (KCS), Pyeongchang, Korea, pp. 633-634, Feb. 20-22, 2008.
[02] Woo Young Choi, Jae Young Song, Jong Pil Kim, Sang Wan Kim , Jong Duk Lee, and Byung-Gook Park, “Reduction of breakdown voltage in I-MOS devices,” IEEK Summer Conference , Jeju, Korea pp. 593-594, Jun. 21-23, 2006.
[01] Jong Pil Kim, Jae Young Song, Woo Young Choi, Sang Wan Kim , Jong Duk Lee, and Byung-Gook Park, “Design and simulation of asymmetric MOSFETs,” IEEK Summer Conference, Jeju, Korea, pp. 577-578, Jun. 21-23, 2006.