International Journal

• [123]
  Seonggeun Kim, Seungwon Go, Sihyun Kim, and Sangwan Kim^*, “Impact of Al-doping on ferroelectricity and reliability of HfZrO film under high temperature annealing,” IEEE Electron Device Letters, Vol. 46, No. 9, pp. 1648-1651, Sep. 2025. [SCIE]
  DOI: 10.1109/LED.2025.3585154
• [122]
  Seungwon Go, Sunwoo Lee, Jaekyun Son, Dong Keun Lee, Hyungju Noh, Jae Yeon Park, Seonggeun Kim, Hyunho Ahn, Sihyun Kim and Sangwan Kim^*, “Demonstration of ferroelectric tunnel field-effect transistor for low power synapse device,” IEEE Transactions on Nanotechnology, Vol. 24, pp. 413-416, Aug. 2025. [SCIE]
  DOI: 10.1109/TNANO.2025.3595532
• [121]
  Jae Yeon Park, Seungwon Go, Dong Keun Lee, Seonggeun Kim, Sihyun Kim^* and Sangwan Kim^*, “Suppression of reverse drain-induced barrier lowering in negative capacitance FETs using a hetero-metal-gate structure,” IEEE Access, Vol. 13, pp. 101781-101788, Jun. 2025. [SCIE] (*co-correspondence)
  DOI: 10.1109/ACCESS.2025.3576583
• [120]
  Jaemin Yeom, Minjeong Ryu, Jae Seung Woo, Jin Wook Lee, Seonggeun Kim, Seungwon Go, Sangwan Kim, and Woo Young Choi^*, “One-ferroelectric-tunnel-FET-based reconfigurable logic gates,” IEEE Transactions on Electron Devices, Vol. 72, No. 6, pp. 3302-3306, Jun. 2025. [SCIE]
  DOI: 10.1109/TED.2025.3561710
• [119]
  Yelim Jeon^#, Hyungju Noh^#, Seungwon Go, and Sangwan Kim^*, “Rigorous analysis on the operating mechanism of gate-injection ferroelectric flash,” Solid-State Electronics, Vol. 228, p. 109153 (1-8), May 2025. [SCIE] (#equally contributed)
  DOI: 10.1016/j.sse.2025.109153
• [118]
  Eungi Hwang, Jang Hyun Kim, Sangwan Kim, and Garam Kim^*, “Multi-level cell structure for capacitor-less 1T DRAM with SiGe-based separated data storing regions,” IEEE Access, Vol. 13, pp. 52528–52537, Mar. 2025. [SCIE]
  DOI: 10.1109/ACCESS.2025.3553802
• [117]
  Jaesung Kim, Seonggeun Kim, Hwijoong Kim, Sangwan Kim^*, Dongil Ho^*, and Choongik Kim^*, “Enhancing AC stress stability in amorphous indium gallium zinc oxide thin-film transistors via controlled hydrogen diffusion,” Journal of Materials Chemistry C, Vol. 13, pp. 3587-3594, Feb. 2025. [SCIE] (*co-correspondence)
  DOI: 10.1039/D4TC04399E
• [116]
  Hyungju Noh, Changmin Chae, Yelim Jeon, Dongseok Oh, and Sangwan Kim^*, “Optimization of cross-bridge Kelvin resistor (CBKR) layout for the precise contact resistance measurement of TiSi2/n⁺ Si,” Electronics, Vol. 14, pp. 762 (1-10), Feb. 2025. [SCIE]
  DOI: 10.3390/electronics14040762

• [115]
  Seungwon Go, Hyungju Noh, Dong Keun Lee, Seonggeun Kim, Jae Yeon Park, Un-hyun Im, Hojoong Lee, Sihyun Kim and Sangwan Kim^*, “Impact of Zr precursor on electrical characteristics of HfZrO laminated structure,” IEEE Electron Device Letters, Vol. 45, No. 10, pp. 2001-2004, Oct. 2024. [SCIE]
  DOI: 10.1109/LED.2024.3435547
• [114]
  Tae Young Yoon, Dong Gyu Park, Seong Yun Kim, Garam Kim, Sangwan Kim^* and Jang Hyun Kim^*, “RC-IGBT snapback suppression using silicon germanium collector regions,” Journal of Power Electronics, Vol. 24, pp. 1660-1669, Jul. 2024. [SCIE] (*co-correspondence)
  DOI: 10.1007/s43236-024-00875-5
• [113]
  Shinhee Kim, Jae Yeon Park, Dong Keun Lee, Hyungju Noh, Tae-Hyeon Kim, Sihyun Kim^* and Sangwan Kim^*, “Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND array operation,” Solid-State Electronics, Vol. 216, p. 108917 (1-7), Jun. 2024. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.sse.2024.108917
• [112]
  Jingyu Park^#, Seungwon Go^#, Wonjun Chae, Chang Il Ryoo, Changwook Kim, Hyungju Noh, Seonggeun Kim, Byung Du Ahn, In-Tak Cho, Pil Sang Yun, Jong Uk Bae, Yoo Seok Park, Sangwan Kim^*, and Dae Hwan Kim^*, “Floating body effect in indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT),” Scientific Reports, Vol. 14, p. 10067 (1-8), May 2024. [SCIE] (#equally contributed, *co-correspondence)
  DOI: 10.1038/s41598-024-60288-z
• [111]
  Tae Hyun Hwang, Sangwan Kim, Garam Kim, Hyunwoo Kim^* and Jang Hyun Kim^*, “Analysis and Prediction of Nanowire TFET’s Work Function Variation,” Journal of Semiconductor Technology and Science, Vol. 24, No. 2, p. 96-104, Apr 2024. [SCIE] (*co-correspondence)
  DOI: 10.5573/JSTS.2024.24.2.96
• [110]
  Hyojin So, Jungwoo Lee, Chandreswar Mahata, Sangwan Kim^*, and Sungjun Kim^*, “Synaptic properties and short-term memory dynamics of TiO2/WOx heterojunction memristor for reservoir computing,” Advanced Materials Technologies, Vol. 9, No. 5, p. 2301390 (1-14), Mar. 2024. [SCIE] (*co-correspondence)
  DOI: 10.1002/admt.202301390
• [109]
  Chandreswar Mahata, Dongyeol Ju, Tanmoy Das, Beomki Jeon, Muhammad Ismail, Sangwan Kim^*, and Sungjun Kim^*, “Artificial synapses based on 2D-layered palladium diselenide heterostructure dynamic memristor for neuromorphic applications,” Nano Energy, Vol. 120, p. 109168 (1-14), Feb. 2024. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.nanoen.2023.109168
• [108]
  Do Gyun An, Garam Kim, Hyunwoo Kim, Sangwan Kim^*, and Jang Hyun Kim^*, “Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation,” Semiconductor Science and Technology, Vol. 39, p. 015006 (1-7), Jan. 2024. [SCIE] (*co-correspondence)
  DOI: 10.1088/1361-6641/ad10c4

• [107]
  Chaewon Yun, Sangwan Kim, Seongjae Cho, Il Hwan Cho, Hyunwoo Kim, Jang Hyun Kim, and Garam Kim, “Optimization of dual-workfunction line tunnel field-effect transistor with island source junction,” Journal of Semiconductor Technology and Science, Vol. 23, No. 4, pp. 207-214, Aug. 2023. [SCIE]
  DOI: 10.5573/JSTS.2023.23.4.207
• [106]
  Young Suh Song, Sangwan Kim, Jang Hyun Kim, Garam Kim, Jong-Ho Lee, and Woo Young Choi, “Enhancement of thermal characteristics and on-current in GAA MOSFET by utilizing Al2O3-based dual-κ spacer structure,” IEEE Transactions on Electron Devices, Vol. 70, No. 1, pp. 343-348, Jan. 2023. [SCIE]
  DOI: 10.1109/TED.2022.3223321

• [105]
  Seungwon Go, Shinhee Kim, Jae Yeon Park, Dong Keun Lee, Hyung Ju Noh, So Ra Park, Yoon Kim, Dae Hwan Kim, and Sangwan Kim^*, “Impact of sidewall spacer materials and gate underlap length on negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET),” Solid-State Electronics, Vol. 198, p. 108483 (1-5), Dec. 2022. [SCIE]
  DOI: 10.1016/j.sse.2022.108483
• [104]
  Seungwon Go, Shinhee Kim, Dong Keun Lee, Jae Yeon Park, Sora Park, Dae Hwan Kim, Garam Kim, and Sangwan Kim^*, “Design optimization of heterojunction 1T DRAM cell with SiGe body/drain for high performance,” Semiconductor Science and Technology, Vol. 37, p. 125010 (1-7), Nov. 7 2022. [SCIE]
  DOI: 10.1088/1361-6641/ac9e17
• [103]
  Ki Yeong Kim, Young Suh Song, Garam Kim, Sangwan Kim^*, and Jang Hyun Kim^*, “Reliable high-voltage drain-extended FinFET with thermoelectric improvement,” IEEE Transactions on Electron Devices, Vol. 69, No. 11, pp. 5985-5990, Nov. 2022. [SCIE] (*co-correspondence)
  DOI: 10.1109/TED.2022.3209141
• [102]
  Young Suh Song, Ki Yeong Kim, Tae Yong Yoon, Seok Jung Kang, Garam Kim, Sangwan Kim, and Jang Hyun Kim, “Reliability improvement of self-heating effect, hot-carrier injection, and on-current variation by electrical/thermal co-design,” Solid-State Electronics, Vol. 197, p. 108436 (1-6), Nov. 2022. [SCIE]
  DOI: 10.1016/j.sse.2022.108436
• [101]
  Kang Lee, Sangwan Kim, Garam Kim and Jang Hyun Kim, “Research of quantized current effect with work function variation in tunnel-field effect transistor,” Journal of Semiconductor Technology and Science, Vol. 22, No. 4, pp. 266-274, Aug. 2022. [SCIE]
  DOI: 10.5573/JSTS.2022.22.4.266
• [100]
  Garam Kim, Jang Hyun Kim^*, and Sangwan Kim^*, “Multi-colour GaN-based LEDs with trench structure,” Japanese Journal of Applied Physics: Regular Papers, Vol. 61, No. 5, p. 050904 (1-3), May 18, 2022. [SCIE]
  DOI: 10.35848/1347-4065/ac671b
• [99]
  Min Gyu Jeon, Kang Lee, Sangwan Kim, Garam Kim and Jang Hyun Kim, “Doping-less Tunnel Field-effect Transistor with a Gate Insulator Stack to Adjust Tunnel Barrier,” Journal of Semiconductor Technology and Science, Vol. 22, No. 2, pp. 61-68, Apr. 2022. [SCIE]
  DOI: 10.5573/JSTS.2022.22.2.61
• [98]
  Soyoun Kim, Kitae Lee, Sihyun Kim, Munhyeon Kim, Jong-Ho Lee, Sangwan Kim, and Byung-Gook Park, “Investigation of device performance for fin angle optimization in FinFET and gate-all-around FETs for 3 nm-node and beyond,” IEEE Transactions on Electron Devices, Vol. 69, No. 4, pp. 2088-2093, Apr. 2022. [SCIE]
  DOI: 10.1109/TED.2022.3154683
• [97]
  Seok Jung Kang, Jang Hyun Kim, Young Suh Song, Seungwon Go, and Sangwan Kim^*, “Investigation of self-heating effects in vertically stacked GAA MOSFET with wrap-around contact,” IEEE Transactions on Electron Devices, Vol. 69, No. 3, pp. 910-914, Mar. 2022. [SCIE]
  DOI: 10.1109/TED.2022.3140283

• [96]
  Mohit Kumar, Jaeseong Lim, Ji-Yong Park, Sangwan Kim^*, and Hyungtak Seo^*, “Ultrafast nanoscale gradient junction self-powered schottky photodetectors for vision-like object classification,” Advanced Optical Materials, Vol. 9, No. 16, p. 2100208 (1-8), Aug. 18, 2021. [SCIE] (*co-correspondence)
  DOI: 10.1002/adom.202100208
• [95]
  Ryoongbin Lee, Junil Lee, Kitae Lee, Soyoun Kim, Hyunho Ahn, Sihyun Kim, Hyun-Min Kim, Changha Kim, Jong-Ho Lee, Sangwan Kim^*, and Byung-Gook Park^*, “Vertically-stacked Si0.2Ge0.8 nanosheet tunnel FET with 70 mV/dec average subthreshold swing,” IEEE Electron Device Letters, Vol. 42, No. 7, pp. 962-965, Jul. 2021. [SCIE] (*co-correspondence)
  DOI: 10.1109/LED.2021.3079246
• [94]
  Shinhee Kim, Seungwon Go, and Sangwan Kim^*, “Simulation study about negative capacitance effects on recessed channel tunnel FET,” Japanese Journal of Applied Physics: Regular Papers, Vol. 60, No. SC, p. SCCE07 (1-7), Apr. 16, 2021. [SCIE]
  DOI: 10.35848/1347-4065/abf2d2
• [93]
  Mohit Kumar, Jaeseong Lim, Hyunwoo Kang, Sangwan Kim^*, and Hyungtak Seo^*, “Photon-triggered self-powered all electronics with graphene-silicon hybrid device,” Nano Energy, Vol. 82, p. 105668 (1-9), Apr. 2021. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.nanoen.2020.105668
• [92]
  Young Suh Song, Sangwan Kim, Garam Kim, Hyunwoo Kim, Jong-Ho Lee, Jang Hyun Kim, and Byung-Gook Park, “Improvement of self-heating effect in Ge vertically stacked GAA nanowire pMOSFET by utilizing Al2O3 for high-performance logic device and electrical/thermal co-design,” Japanese Journal of Applied Physics: Regular Papers, Vol. 60, No. SC, p. SCCE04 (1-9), Mar. 25, 2021. [SCIE]
  DOI: 10.35848/1347-4065/abec5c
• [91]
  Mohit Kumar, Chaitali Jagannath Pawase, Hyobin Choi, Sangwan Kim^*, and Hyungtak Seo^*, “Light‐regulated mott transition for on‐demand multilevel memory storage, processing, and energy efficient machine vision,” Advanced Electronic Materials, Vol. 7, No. 4, p. 2001118 (1-7), Mar. 15, 2021. [SCIE] (*co-correspondence)
  DOI: 10.1002/aelm.202001118
• [90]
  Mohit Kumar, Heecheol Shin, Hyobin Choi, Ji-Yong Park, Sangwan Kim^*, and Hyungtak Seo^*, “Point-contact enabled reliable and low-voltage memristive switching and artificial synapse from highly transparent all-oxide-integration,” Journal of Alloys and Compounds, Vol. 857, No. 15, p. 157593 (1-7), Mar. 2021. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.jallcom.2020.157593
• [89]
  Young Suh Song, Jang Hyun Kim, Garam Kim, Hyun-Min Kim, Sangwan Kim^*, and Byung-Gook Park^*, “Improvement in self-heating characteristic by incorporating hetero-gate-dielectric in gate-all-around MOSFETs,” IEEE Journal of the Electron Devices Society, Vol. 9, No. 1, pp. 36-41, Jan. 2021. [SCIE]
  DOI: 10.1109/JEDS.2020.3038391
• [88]
  Shinhee Kim, Jae Yeon Park, Seungwon Go, Hyug Su Kwon, Woo Young Choi, and Sangwan Kim^*, “A low-power nanoelectromechanical (NEM) device with Al-doped HfO2-based ferroelectric capacitor,” Solid-State Electronics, Vol. 175, p. 107956 (1-6), Jan. 2021. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.sse.2021.107956

• [87]
  Mohit Kumar, Hyobin Choi, Jaeseong Lim, Ji-Yong Park, Sangwan Kim^*, and Hyungtak Seo^*, “Broadband alternating current photovoltaic effect: An application for high-performance sensing and imaging body aches,” Nano Energy, Vol. 77, p. 105240 (1-10), Nov. 2020. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.nanoen.2020.105240
• [86]
  Mohit Kumar, Jaeseong Lim, Ji-Yong Park, Sangwan Kim^*, and Hyungtak Seo^*, “Electric-field-induced healing of inanimate topographies: multistate resistive switching and nano-sized artificial synapse functionality,” Applied Surface Science, Vol. 530, No. 15, p. 147190 (1-7), Nov. 2020. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.apsusc.2020.147190
• [85]
  Jang Hyun Kim, Tae Chan Kim, Garam Kim, Hyun Woo Kim, and Sangwan Kim^*, “Methodology to investigate impact of grain orientation on threshold voltage and current variability in tunneling field-effect transistors,” IEEE Journal of the Electron Devices Society, Vol. 8, No. 1, pp. 1345-1349, Oct. 2020. [SCIE]
  DOI: 10.1109/JEDS.2020.3033313
• [84]
  Mohit Kumar, Ranveer Singh, Hyunwoo Kang, Ji-Yong Park, Sangwan Kim, and Hyungtak Seo^*, “Brain-like spatiotemporal information processing with nanosized second-order synaptic emulators; “solid-state memory visualizer”,” Nano Energy, Vol. 76, p. 105014 (1-8), Oct. 2020. [SCIE]
  DOI: 10.1016/j.nanoen.2020.105014
• [83]
  Mohit Kumar, Jaeseong Lim, Sangwan Kim^*, and Hyungtak Seo^*, “Environment-adaptable photonic-electronic-coupled neuromorphic angular visual system,” ACS Nano, Vol. 14, No. 10, p. 14108-14117, Sep. 28, 2020. [SCIE] (*co-correspondence)
  DOI: 10.1021/acsnano.0c06874
• [82]
  Garam Kim, Jang Hyun Kim, and Sangwan Kim^*, “Optimization of spacer and source/channel junction to improve TFET characteristics,” IEICE Electronics Express, Vol. 17, No. 17, pp. 20200211 (1-5), Sep. 10, 2020. [SCIE]
  DOI: 10.1587/elex.17.20200211
• [81]
  Jang Hyun Kim, Hyun Woo Kim, Young Suh Song, Sangwan Kim^*, and Garam Kim^*, “Analysis of current variation with work function variation in L-shaped tunnel-field effect transistor,” Micromachines, Vol. 11, No. 8, p. 780 (1-10), Aug. 2020. [SCIE] (*co-correspondence)
  DOI: 10.3390/mi11080780
• [80]
  Garam Kim, Jang Hyun Kim, Jaemin Kim, and Sangwan Kim^*, “Analysis of work-function variation effects in a tunnel field-effect transistor depending on the device structure,” Applied Sciences, Vol. 10, No. 15, p. 5378 (1-10), Aug. 2020. [SCIE]
  DOI: 10.3390/app10155378
• [79]
  Seok Jung Kang, Jeong-Uk Park, Kyung Jin Rim, Yoon Kim, Jang Hyun Kim, Garam Kim, and Sangwan Kim^*, “Analysis of channel area fluctuation effects of gate-all-around tunnel field-effect transistor,” Journal of Nanoscience and Nanotechnology, Vol. 20, No. 7, pp. 4409-4413, Jul. 2020. [SCIE]
  DOI: 10.1166/jnn.2020.17792
• [78]
  Ryoongbin Lee, Junil Lee, Kitae Lee, Soyoun Kim, Sihyun Kim, Sangwan Kim, and Byung-Gook Park, “I-shaped SiGe fin tunnel field-effect transistor with high ION/IOFF ratio,” Journal of Nanoscience and Nanotechnology, Vol. 20, No. 7, pp. 4298-4302, Jul. 2020. [SCIE]
  DOI: 10.1166/jnn.2020.17794
• [77]
  Ye Sung Kwon, Seong-Hyun Lee, Yoon Kim, Garam Kim, Jang Hyun Kim, and Sangwan Kim^*, “Surrounding channel nanowire tunnel field-effect transistor with dual gate to reduce a hump phenomenon,” Journal of Nanoscience and Nanotechnology, Vol. 20, No. 7, pp. 4182-4187, Jul. 2020. [SCIE]
  DOI: 10.1166/jnn.2020.17793
• [76]
  Sihyun Kim, Munhyeon Kim, Donghyun Ryu, Kitae Lee, Soyoun Kim, Junil Lee, Ryoongbin Lee, Sangwan Kim, Jong-Ho Lee, and Byung-Gook Park, “Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs,” IEEE Transactions on Electron Devices, Vol. 67, No. 6, pp. 2648-2652, Jun. 2020. [SCIE]
  DOI: 10.1109/TED.2020.2989416
• [75]
  Seung-Hyun Lee, Jeong-Uk Park, Garam Kim, Dong-Woo Jee, Jang Hyun Kim^*, and Sangwan Kim^*, “Rigorous study on hump phenomena in surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET),” Applied Sciences, Vol. 10, No. 10, p. 3596 (1-9), May 2020. [SCIE] (*co-correspondence)
  DOI: 10.3390/app10103596
• [74]
  Faraz Najam, Sangwan Kim, Woo Young Choi, and Yun Seop Yu, “Physically consistent method for calculating trap-assisted-tunneling current applied to line tunneling field-effect transistor,” IEEE Transactions on Electron Devices, Vol. 67, No. 5, pp. 2106-2112, May 2020. [SCIE]
  DOI: 10.1109/TED.2020.2982262
• [73]
  Jang Hyun Kim and Sangwan Kim^*, “Study on the nonlinear output characteristic of tunnel field-effect transistor,” Journal of Semiconductor Technology and Science, Vol. 20, No. 2, pp. 158-162, Apr. 2020. [SCIE]
  DOI: 10.5573/JSTS.2020.20.2.158
• [72]
  Mohit Kumar, Ranveer Singh, Hyunwoo Kang, Sangwan Kim^*, and Hyungtak Seo^*, “An artificial piezotronic synapse for tactile perception,” Nano Energy, Vol. 73, p. 104756 (1-9), Apr. 2020. [SCIE] (*co-correspondence)
  DOI: 10.1016/j.nanoen.2020.104756
• [71]
  Donghyun Ryu, Munhyeon Kim, Junsu Yu, Sangwan Kim, Jong-Ho Lee, and Byung-Gook Park, “Investigation of sidewall high-k interfacial layer effect in gate-all-around structure,” IEEE Transactions on Electron Devices, Vol. 67, No. 4, pp. 1859-1863, Apr. 2020. [SCIE]
  DOI: 10.1109/TED.2020.2975255
• [70]
  Kitae Lee, Junil Lee, Sihyun Kim, Ryoongbin Lee, Soyoun Kim, Munhyeon Kim, Jong-Ho Lee, Sangwan Kim^*, and Byung-Gook Park^*, “Negative capacitance effect on MOS structure: influence of electric field variation,” IEEE Transactions on Nanotechnology, Vol. 19, No. 1, pp. 168-171, Feb. 14, 2020. [SCIE] (*co-correspondence)
  DOI: 10.1109/TNANO.2020.2972605
• [69]
  Junil Lee, Ryoongbin Lee, Sihyun Kim, Kitae Lee, Hyun-Min Kim, Soyoun Kim, Munhyeon Kim, Sangwan Kim, Jong-Ho Lee, and Byung-Gook Park, “Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique,” Solid-State Electronics, Vol. 164, p. 107701 (1-5), Feb. 2020. [SCIE]
  DOI: 10.1016/j.sse.2019.107701
• [68]
  Yunho Choi, Kitae Lee, Kyoung Yeon Kim, Sihyun Kim, Junil Lee, Ryoongbin Lee, Hyun-Min Kim, Young Suh Song, Sangwan Kim, Jong-Ho Lee, and Byung-Gook Park, “Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET,” Solid-State Electronics, Vol. 164, p. 107686 (1-5), Feb. 2020. [SCIE]
  DOI: 10.1016/j.sse.2019.107686
• [67]
  Jang Hyun Kim, Min Gyu Lee, Seong-Su Shin, and Sangwan Kim^*, “Investigation of line-edge roughness effects on electrical characteristics of nanowire tunnel FETs and MOSFETs,” Journal of Semiconductor Technology and Science, Vol. 20, No. 1, pp. 41-46, Feb. 2020. [SCIE]
  DOI: 10.5573/JSTS.2020.20.1.041

• [66]
  Jaehong Lee#, Garam Kim#, and Sangwan Kim^*, “Effects of back-gate bias on subthreshold swing of tunnel field-effect transistor,” Electronics, Vol. 8, No. 12, p. 1415 (1-7), Nov. 2019. [SCIE]
  DOI: 10.3390/electronics8121415
• [65]
  Seunghyun Yun, Jeongmin Oh, Seokjung Kang, Yoon Kim, Jang Hyun Kim, Garam Kim, and Sangwan Kim^*, “F-shaped tunnel field-effect transistor (TFET) for the low-power application,” Micromachines, Vol. 10, No. 11, p. 760 (1-10), Nov. 2019. [SCIE]
  DOI: 10.3390/mi10110760
• [64]
  Junsu Yu, Sihyun Kim, Donghyun Ryu, Kitae Lee, Changha Kim, Jong-Ho Lee, Sangwan Kim^*, and Byung-Gook Park^*, “Investigation on ambipolar current suppression using stacked gate in L-shaped tunnel field-effect transistor,” Micromachines, Vol. 10, No. 11, p. 753 (1-9), Nov. 2019. [SCIE] (*co-correspondence)
  DOI: 10.3390/mi10110753
• [63]
  Jang Hyun Kim and Sangwan Kim^*, “Investigation on temperature dependency of recessed-channel reconfigurable field-effect transistor,” Electronics, Vol. 8, No. 10, p. 1124 (1-6), Oct. 2019. [SCIE]
  DOI: 10.3390/electronics8101124
• [62]
  Jang Hyun Kim, Hyun Woo Kim, Seong-Su Shin, Sangwan Kim^*, and Byung-Gook Park^*, “Transient analysis of tunnel field-effect transistor with raised drain,” Journal of Nanoscience and Nanotechnology, Vol. 19, No. 10, pp. 6212-6216, Oct. 2019. [SCIE] (*co-correspondence)
  DOI: 10.1166/jnn.2019.17018
• [61]
  Kitae Lee, Junil Lee, Sihyun Kim, Euyhwan Park, Ryoongbin Lee, Hyun-Min Kim, Sangwan Kim^*, and Byung-Gook Park^*, “Tunnel field effect transistor with ferroelectric gate insulator,” Journal of Nanoscience and Nanotechnology, Vol. 19, No. 10, pp. 6095-6098, Oct. 2019. [SCIE] (*co-correspondence)
  DOI: 10.1166/jnn.2019.16994
• [60]
  Ryoongbin Lee, Kitae Lee, Sihyun Kim, Dae Woong Kwon, Sangwan Kim^*, and Byung-Gook Park^*, “Nonvolatile memory (NVM) operation of tunnel field-effect transistor (TFET) using ferroelectric HfO>2 sidewall,” Journal of Nanoscience and Nanotechnology, Vol. 19, No. 10, pp. 6061-6065, Oct. 2019. [SCIE] (*co-correspondence)
  DOI: 10.1166/jnn.2019.17001
• [59]
  Korok Chatterjee, Sangwan Kim, Golnaz Karbasian, Daewoong Kwon, Ava J. Tan, Ajay K. Yadav, Claudy R. Serrao, Chenming Hu, and Sayeef Salahuddin, “Challenges to partial switching of Hf0.8Zr0.2O2 gated ferroelectric FET for multilevel/analog or low-voltage memory operation,” IEEE Electron Device Letters, Vol. 40, No. 9, pp. 1423-1426, Sep. 2019. [SCI]
  DOI: 10.1109/LED.2019.2931430
• [58]
  Seong Su Shin#, Jang Hyun Kim#, and Sangwan Kim^*, “L-shaped tunnel FET with stacked gates to suppress the corner effect,” Japanese Journal of Applied Physics: Regular Papers, Vol. 58, No. SD, p. SDDE10 (1-6), Jun. 01 2019. [SCI]
  DOI: 10.7567/1347-4065/ab0ff1
• [57]
  Jang Hyun Kim, Jeesoo Chang, Sangwan Kim^*, and Byung-Gook Park^*, “Oxide thin film transistor with a novel gate insulator stack to suppress photo-excited charge injection,” IEEE Transactions on Nanotechnology, Vol. 18, No. 1, pp. 491-493, May 2019. [SCI] (*co-correspondence)
  DOI: 10.1109/TNANO.2019.2915170
• [56]
  Jang Hyun Kim, Sangwan Kim^*, and Byung-Gook Park^*, “Double-gate TFET with vertical channel sandwiched by lightly doped Si,” IEEE Transactions on Electron Devices, Vol. 66, No. 4, pp. 1656-1661, Apr. 2019. [SCI] (*co-correspondence)
  DOI: 10.1109/TED.2019.2899206
• [55]
  Hwa Young Gu and Sangwan Kim^*, “Design optimization of double-gate isosceles trapezoid tunnel field-effect transistor (DGIT-TFET),” Micromachines, Vol. 10, No. 4, p. 229 (1-10), Mar. 30 2019. [SCIE]
  DOI: 10.3390/mi10040229
• [54]
  Junil Lee, Ryoongbin Lee, Sihyun Kim, Euyhwan Park, Hyun-Min Kim, Kitae Lee, Sangwan Kim^*, and Byung-Gook Park^*, “Fabrication methods for nanowire tunnel FET with locally concentrated silicon-germanium channel,” Journal of Semiconductor Technology and Science, Vol. 19, No. 1, pp. 18-23, Feb. 2019. [SCIE] (*co-correspondence)
  DOI: 10.5573/JSTS.2019.19.1.018
• [53]
  Garam Kim, Jaehong Lee, Jang Hyun Kim, and Sangwan Kim^*, “High on-current Ge-channel heterojunction tunnel field-effect transistor using direct band-to-band tunneling,” Micromachines, Vol. 10, No. 2, p. 77 (1-8), Jan. 24 2019. [SCIE]
  DOI: 10.3390/mi10020077
• [52]
  Jang Hyun Kim, Hyun Woo Kim, Garam Kim, Sangwan Kim^*, and Byung-Gook Park^*, “Demonstration of fin-tunnel field-effect transistor with elevated drain,” Micromachines, Vol. 10, No. 1, p. 30 (1-10), Jan. 07 2019. [SCIE] (*co-correspondence)
  DOI: 10.3390/mi10010030

• [51]
  Sangwan Kim and Woo Young Choi, “Compact potential model for Si1-xGex/Si heterojunction double-gate tunnel field-effect transistors (TFET),” Journal of Nanoscience and Nanotechnology, Vol. 18, No. 9, pp. 5953-5958, Sep. 2018. [SCIE]
  DOI: 10.1166/jnn.2018.15578
• [50]
  Hyungjin Kim, Sihyun Kim, Hyun-Min Kim, Kitae Kim, Sangwan Kim, and Byung-Gook Park, “A 1T dynamic random access memory cell based on gated thyristor with surrounding gate structure for high scalability,” Journal of Nanoscience and Nanotechnology, Vol. 18, No. 9, pp. 5919-5924, Sep. 2018. [SCIE]
  DOI: 10.1166/jnn.2018.15569
• [49]
  Hyun-Min Kim, Dae Woong Kwon, Sihyun Kim, Kitae Lee, Junil Lee, Euyhwan Park, Ryoongbin Lee, Hyungjin Kim, Sangwan Kim, and Byung-Gook Park, “Volatile and nonvolatile characteristics of asymmetric dual-gate thyristor RAM fabricated vertically with polycrystalline silicon,” Journal of Nanoscience and Nanotechnology, Vol. 18, No. 9, pp. 5882-5886, Sep. 2018. [SCIE]
  DOI: 10.1166/jnn.2018.15570
• [48]
  Sihyun Kim, Dae Woong Kwon, Sangwan Kim, Ryoongbin Lee, Tae-Hyeon Kim, Hyun-Sun Mo, Dae Hwan Kim, and Byung-Gook Park, “Analysis of current drift on p-channel pH-sensitive SiNW ISFET by capacitance measurement,” Current Applied Physics, Vol. 18, pp. S68-S74, Aug. 2018. [SCI]
  DOI: 10.1016/j.cap.2017.11.021
• [47]
  Sangwook Kim and Sangwan Kim^*, “High-performance recessed-channel reconfigurable field-effect transistor using Si-Ge heterojunction,” Journal of Semiconductor Technology and Science, Vol. 18, No. 3, pp. 392-395, Jun. 2018. [SCIE]
  DOI: 10.5573/JSTS.2018.18.3.392
• [46]
  Sangwan Kim, Woo Young Choi, and Byung-Gook Park, “Vertical-structured electron-hole bilayer tunnel field-effect transistor for extremely low-power operation with high scalability,” IEEE Transactions on Electron Devices, Vol. 65, No. 5, pp. 2010-2015, May 2018. [SCI]
  DOI: 10.1109/TED.2018.2817569
• [45]
  Dae Woong Kwon, Junil Lee, Sihyun Kim, Ryoongbin Lee, Sangwan Kim, Jong-Ho Lee, and Byung-Gook Park, “Novel boosting scheme using asymmetric pass voltage for reducing program disturbance in 3-dimensional NAND flash memory,” IEEE Journal of the Electron Devices Society, Vol. 6, No. 1, pp. 286-290, Feb. 2018. [SCIE]
  DOI: 10.1109/JEDS.2018.2801219
• [44]
  Ava J. Tan, Ajay K. Yadav, Korok Chatterjee, Daewoong Kwon, Sangwan Kim, Chenming Hu, and Sayeef Salahuddin, “A nitrided interfacial oxide for interface state improvement in hafnium zirconium oxide-based ferroelectric transistor technology,” IEEE Electron Device Letters, Vol. 39, No. 1, pp. 95-98, Jan. 2018. [SCI]
  DOI: 10.1109/LED.2017.2772791

• [43]
  Ryoongbin Lee, Dae Woong Kwon, Sihyun Kim, Sangwan Kim, Hyun-Sun Mo, Dae Hwan Kim, and Byung-Gook Park, “Nanowire size dependence on sensitivity of silicon nanowire field-effect transistor-based pH sensor,” Japanese Journal of Applied Physics: Regular Papers, Vol. 56, No. 12, pp. 124001 (1-6), Nov. 20 2017. [SCI]
  DOI: 10.7567/JJAP.56.124001
• [42]
  Won Joo Lee, Hee Tae Kwon, Hyun-Suk Choi, Deahoon Wee, Sangwan Kim^*, and Yoon Kim^*, “Reconfigurable U-shaped tunnel field-effect transistor,” IEICE Electronics Express, Vol. 14, No. 20, pp. 20170758 (1-11), Oct. 04 2017. [SCIE] (*co-correspondence)
  DOI: 10.1587/elex.14.20170758
• [41]
  Dae Woong Kwon, Jang Hyun Kim, Euyhwan Park, Junil Lee, Sangwan Kim, and Byung-Gook Park, “Switching characteristic analysis of tunnel field-effect transistor (TFET) inverters,” Journal of Nanoscience and Nanotechnology, Vol. 17, No. 10, pp. 7134-7139, Oct. 01 2017. [SCIE]
  DOI: 10.1166/jnn.2017.14714
• [40]
  Korok Chatterjee#, Sangwan Kim#, Golnaz Karbasian, Ava J. Tan, Ajay K. Yadav, Asif I. Khan, Chenming Hu, and Sayeef Salahuddin, “Self-aligned, gate last, FDSOI, ferroelectric gate memory device with 5.5 nm Hf0.8Zr0.2O2, high endurance and breakdown recovery,” IEEE Electron Device Letters, Vol. 38, No. 10, pp.1379-1382, Oct. 2017. [SCI]
  DOI: 10.1109/LED.2017.2748992
• [39]
  Habeom Lee, Junyeob Yeo, Jinhwan Lee, Hyunmin Cho, Jinhyeong Kwon, Seungyong Han, Sangwan Kim, Sukjoon Hong, and Seung Hwan Ko, “Selective thermochemical growth of hierarchical ZnO nanowire branches on silver nanowire backbone percolation network heaters,” Journal of Physical Chemistry C, Vol. 121, No. 40, pp. 22542-22549, Sep. 2017. [SCI]
  DOI: 10.1021/acs.jpcc.7b08129
• [38]
  Sangwan Kim and Woo Young Choi, “Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field,” Japanese Journal of Applied Physics: Regular Papers, Vol. 56, No. 8, pp. 084301-1-084301-5, Jul. 2017. [SCI]
  DOI: 10.7567/JJAP.56.084301
• [37]
  Dae Woong Kwon, Hyun Woo Kim, Jang Hyun Kim, Euyhwan Park, Junil Lee, Wandong Kim, Sangwan Kim, Jong-Ho Lee, and Byung-Gook Park, “Effects of localized body doping on switching characteristics of tunnel field-effect transistor (TFET) inverters with vertical structures,” IEEE Transactions on Electron Devices, Vol. 64, No. 4, pp. 1799-1805, Apr. 2017. [SCI]
  DOI: 10.1109/TED.2017.2669365
• [36]
  Peng Zheng^*, Sangwan Kim^*, Daniel Connelly, Kimihiko Kato, Fei Ding, Lenonard Rubin, and Tsu-Jae King Liu, “Sub-lithographic patterning via tilted ion implantation for scaling beyond the 7 nm technology node,” IEEE Transactions on Electron Devices, Vol. 64, No. 1, pp. 231-236, Jan. 2017. [SCI] (*co-correspondence)
  DOI: 10.1109/TED.2016.2622284

• [35]
  Hui Tae Kwon, Sangwan Kim, Won Joo Lee, Daehoon Wee, and Yoon Kim, “A recessed-channel tunnel field-effect transistor (RTFET) with the asymmetric source and drain,” Journal of Semiconductor Technology and Science, Vol. 16, No. 5, pp. 635-640, Oct. 2016. [SCIE]
  DOI: 10.5573/JSTS.2016.16.5.635
• [34]
  Sangwook Kim and Sangwan Kim^*, “Recessed-channel reconfigurable field-effect transistor,” Electronics Letters, Vol. 52, No. 19, pp. 1640-1642, Sep. 2016. [SCI]
  DOI: 10.1049/el.2016.2401
• [33]
  Sangwan Kim^*, Peng Zheng, Kimihiko Kato, Leonard Rubin, and Tsu-Jae King Liu, “Tilted ion implantation as a cost-efficient sublithographic patterning technique,” Journal of Vacuum Science and Technology B, Vol. 34, No. 4, pp. 040608-1-040608-5, Jul./Aug. 2016. [SCI]
  DOI: 10.1116/1.4953085
• [32]
  Dae Woong Kwon, Jang Hyun Kim, Wandong Kim, Sangwan Kim, Jong-Ho Lee, and Byung-Gook Park, “Analysis on trapping kinetics of stress-induced trapped holes in gate dielectric of HfInZnO amorphous oxide TFT,” IEEE Transactions on Electron Devices, Vol. 63, No. 6, pp. 2398-2404, Jun. 2016. [SCI]
  DOI: 10.1109/TED.2016.2555332
• [31]
  Sangwan Kim and Woo Young Choi, “Hump effects of Germanium / Silicon heterojunction tunnel field-effect transistors,” IEEE Transactions on Electron Devices, Vol. 63, No. 6, pp. 2583-2588, Jun. 2016. [SCI]
  DOI: 10.1109/TED.2016.2555928
• [30]
  Sangwan Kim, Min-Chul Sun, Euyhwan Park, Jang Hyun Kim, Dae Woong Kwon, and Byung-Gook Park, “Improvement of current drivability in high-scalable tunnel field-effect transistors with CMOS compatible self-aligned process,” Electronics Letters, Vol. 52, No. 12, pp. 1071-1072, Jun. 2016. [SCI]
  DOI: 10.1049/el.2016.0707
• [29]
  Sangwan Kim, Jang Hyun Kim, Tsu-Jae King Liu, Woo Young Choi, and Byung-Gook Park, “Demonstration of L-shaped tunnel field-effect transistors,” IEEE Transactions on Electron Devices, Vol. 63, No. 4, pp. 1774-1778, Apr. 2016. [SCI]
  DOI: 10.1109/TED.2015.2472496

• [28]
  Jang Hyun Kim, Sangwan Kim, Hyun Woo Kim, and Byung-Gook Park, “Vertical type double gate tunneling FET with thin tunnel barrier,” Electronics Letters, Vol. 51, No. 9, pp. 718-720, Apr. 2015. [SCI]
  DOI: 10.1049/el.2014.3864

• [27]
  Hyun Woo Kim, Jong Pil Kim, Sangwan Kim, Min-Chul Sun, Garam Kim, Jang Hyun Kim, Euyhwan Park, Hyungjin Kim, and Byung-Gook Park, “Schottky barrier tunnel field-effect transistor using spacer technique,” Journal of Semiconductor Technology and Science, Vol. 14, No. 5, pp. 572-578, Oct. 2014. [SCIE]
  DOI: 10.5573/JSTS.2014.14.5.572
• [26]
  Garam Kim, Sangwan Kim, Jang Hyun Kim, Euyhwan Park, and Byung-Gook Park, “Effects of periodic trench structure on the cathodo-luminescence in InGaN/GaN multi-quantum-wells,” Electronics Letters, Vol. 50, No. 14, pp. 1012-1014, Jul. 2014. [SCI]
  DOI: 10.1049/el.2014.1567
• [25]
  Hyun Woo Kim, Jang Hyun Kim, Sangwan Kim, Min-Chul Sun, Euyhwan Park, and Byung-Gook Park, “Tunneling field-effect transistor with Si/SiGe material for high current drivability,” Japanese Journal of Applied Physics: Regular Papers, Vol. 53, No. 6S, pp. 06JE12-1–06JE12-4, May 2014. [SCI]
  DOI: 10.7567/JJAP.53.06JE12
• [24]
  Min-Chul Sun, Hyun Woo Kim, Hyungjin Kim, Sangwan Kim, Garam Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “VT-modulation of planar tunnel field-effect transistors with ground-plane under ultrathin body and bottom oxide,” Journal of Semiconductor Technology and Science, Vol. 14, No. 2, pp. 139-145, Apr. 2014. [SCIE]
  DOI: 10.5573/JSTS.2014.14.2.139

• [23]
  Min-Chul Sun, Garam Kim, Jung Han Lee, Hyungjin Kim, Sangwan Kim, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Patterning of Si nanowire array with electron beam lithography for sub-22 nm Si nanoelectronics technology,” Microelectronic Engineering, Vol. 110, pp. 141-146, Oct. 2013. [SCI]
  DOI: 10.1016/j.mee.2013.03.023
• [22]
  Sangwan Kim, Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, “Investigation on the corner effect of L-shaped tunneling field-effect transistors and their fabrication method,” Journal of Nanoscience and Nanotechnology, Vol. 13, No. 9, pp. 6376-6381, Sep. 2013. [SCI]
  DOI: 10.1166/jnn.2013.7609
• [21]
  Min-Chul Sun, Sangwan Kim, Hyun Woo Kim, Hyungjin Kim, and Byung-Gook Park, “Complementary-metal-oxide-semiconductor technology-compatible tunneling field-effect transistors with 14 nm gate, sigma-shape source, and recessed channel,” Japanese Journal of Applied Physics: Regular Papers, Vol. 52, No. 6, pp. 06GE06-1–06GE06-5, Jun. 2013. [SCI]
  DOI: 10.7567/JJAP.52.06GE06
• [20]
  Sangwan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “L-shaped tunneling field-effect transistors for complementary logic applications,” IEICE Transactions on Electronics, Vol. E96-C, No. 5, pp. 634-638, May 2013. [SCIE]
  DOI: 10.1587/transele.E96.C.634
• [19]
  Min-Chul Sun, Sangwan Kim, Garam Kim, Hyun Woo Kim, Hyungjin Kim, and Byung-Gook Park, “Novel tunneling field-effect transistor with sigma-shape embedded SiGe sources and recessed channel,” IEICE Transactions on Electronics, Vol. E96-C, No. 5, pp. 639-643, May 2013. [SCIE]
  DOI: 10.1587/transele.E96.C.639

• [18]
  Hyun Woo Kim, Jang Hyun Kim, Sangwan Kim, Min-Chul Sun, Garam Kim, Euyhwan Park, Hyungjin Kim, Kyung Wan Kim, and Byung-Gook Park, “A novel fabrication method for the nanoscale tunneling field effect transistor,” Journal of Nanoscience and Nanotechnology, Vol. 12, No. 7, pp. 5592-5597, Jul. 2012. [SCI]
  DOI: 10.1166/jnn.2012.6261
• [17]
  Min-Chul Sun, Garam Kim, Sangwan Kim, Hyun Woo Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Co-Integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology,” Journal of Nanoscience and Nanotechnology, Vol. 12, No. 7, pp. 5313-5317, Jul. 2012. [SCI]
  DOI: 10.1166/jnn.2012.6226
• [16]
  Sangwan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Design guideline of Si-based L-shaped tunneling field-effect transistors,” Japanese Journal of Applied Physics: Regular Papers, Vol. 51, No. 6, pp. 06FE09-1–06FE09-4, Jun. 2012. [SCI]
  DOI: 10.1143/JJAP.51.06FE09
• [15]
  Min-Chul Sun, Hyun Woo Kim, Sangwan Kim, Garam Kim, Hyungjin Kim, and Byung-Gook Park, “Comparative study on top- and bottom-source vertical-channel tunnel field-effect transistors,” IEICE Transactions on Electronics, Vol. E95-C, No. 5, pp. 826-830, May 2012. [SCIE]
  DOI: 10.1587/transele.E95.C.826
• [14]
  Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, Sangwan Kim, Garam Kim, and Byung-Gook Park, “Study on threshold voltage control of tunnel field-effect transistors using VT-control doping region,” IEICE Transactions on Electronics, Vol. E95-C, No. 5, pp. 820-825, May 2012. [SCIE]
  DOI: 10.1587/transele.E95.C.820
• [13]
  Min-Chul Sun, Sangwan Kim, Hyun Woo Kim, Garam Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, “Design of thin-body double-gated vertical-channel tunneling field-effect transistors for ultralow-power logic circuits,” Japanese Journal of Applied Physics: Regular Papers, Vol. 51, No. 4, pp. 04DC03-1–04DC03-5, Apr. 2012. [SCI]
  DOI: 10.1143/JJAP.51.04DC03

• [12]
  Garam Kim, Sangwan Kim, Kyung-Chang Ryoo, Jeong-Hoon Oh, Min-Chul Sun, Hyun Woo Kim, Dae Woong Kwon, Jisoo Chang, Sunghun Jung, and Byung-Gook Park, “Split-gate-structure 1T DRAM for retention characteristic improvement,” Journal of Nanoscience and Nanotechnology, Vol. 11, No. 7, pp. 5603-5607, Jul. 2011. [SCI]
  DOI: 10.1166/jnn.2011.4333
• [11]
  Jang Hyun Kim, Dae Woong Kwon, Jisoo Chang, Sangwan Kim, Jae Chul Park, Chang Jung Kim, and Byung-Gook Park, “Investigation on the characteristics of stress-induced hump in amorphous oxide thin film transistors,” Applied Physics Letters, Vol. 99, No. 7, pp. 043502-1–043502-3, Jul. 2011. [SCI]
  DOI: 10.1063/1.3606538
• [10]
  Dae Woong Kwon, Jang Hyun Kim, Jisoo Chang, Sangwan Kim, Wandong Kim, Jae Chul Park, Chang Jung Kim, and Byung-Gook Park, “Light effect on negative bias-induced instability of HfInZnO amorphous oxide thin-film transistor,” IEEE Transactions on Electron Devices, Vol. 58, No. 4, pp. 1127-1133, Apr. 2011. [SCI]
  DOI: 10.1109/TED.2011.2109388
• [9]
  Dae Woong Kwon, Jang Hyun Kim, Jisoo Chang, Sangwan Kim, Wandong Kim, Jae Chul Park, Ihun Song, Chang Jung Kim, U In Jung, and Byung-Gook Park, “Temperature effect on negative bias-induced instability of HfInZnO amorphous oxide thin film transistor,” Applied Physics Letters, Vol. 98, No. 6, pp. 0635021–0635023, Feb. 2011. [SCI]
  DOI: 10.1063/1.3549180

• [8]
  Seongjae Cho, Shinichi O'uchi, Kazuhiko Endo, Sangwan Kim, Younghwan Son, In Man Kang, Meishoku Masahara, James S. Harris Jr., and Byung-Gook Park, “Rigorous design of 22-nm node 4-terminal SOI FinFETs for reliable low standby power operation with semi-empirical parameters,” Journal of Semiconductor Technology and Science, Vol. 10, No. 4, pp. 265-275, Dec. 2010. [SCIE]
  DOI: 10.5573/JSTS.2010.10.4.265
• [7]
  Dae Woong Kwon, Jang Hyun Kim, Jisoo Chang, Sangwan Kim, Min-Chul Sun, Garam Kim, Hyun Woo Kim, Jae Chul Park, Ihun Song, Chang Jung Kim, U In Jung, and Byung-Gook Park, “Charge injection from gate electrode by simultaneous stress of optical and electrical biases in HfInZnO amorphous oxide thin film transistor,” Applied Physics Letters, Vol. 97, No. 19, pp. 1935041–1935043, Nov. 2010. [SCI]
  DOI: 10.1063/1.3508955
• [6]
  Jae Young Song, Jong Pil Kim, Sangwan Kim, Jeong-Hoon Oh, Kyung-Chang Ryoo, Min-Chul Sun, Garam Kim, Jang-Gn Yun, Hyungcheol Shin, and Byung-Gook Park, “Fin and recess-channel metal oxide semiconductor field effect transistor for sub-50 nm dynamic random access memory cell,” Japanese Journal of Applied Physics: Regular Papers, Vol. 49, No. 10, pp. 1042021–1042025, Oct. 2010. [SCI]
  DOI: 10.1143/JJAP.49.104202
• [5]
  Jae Hyun Park, Jae Young Song, Jong Pil Kim, Sangwan Kim, Jang-Gn Yun, and Byung-Gook Park, “Fabrication of highly scaled silicon nanowire gate-all-around metal-oxide-semiconductor field effect transistors by using self-aligned local-channel V-gate by optical lithography process,” Japanese Journal of Applied Physics: Regular Papers, Vol. 49, No. 8, pp. 842031–842035, Aug. 2010. [SCI]
  DOI: 10.1143/JJAP.49.084203

• [4]
  Jong Pil Kim, Jae Young Song, Sangwan Kim, Jae Hyun Park, Woo Young Choi, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, “Self-aligned asymmetric metal-oxide-semiconductor field effect transistors fabricated on silicon-on-insulator,” Japanese Journal of Applied Physics, Vol. 48, No. 9, pp. 091201-1–091201-5, Sep. 24, 2009. [SCI]
  DOI: 10.1143/JJAP.48.091201

• [3]
  Jong Pil Kim, Woo Young Choi, Jae Young Song, Sangwan Kim, Jong Duk Lee, and Byung-Gook Park, “Design and fabrication of asymmetric MOSFETs using a novel self-aligned structure,” IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2969-2974, Nov. 2007. [SCI]
  DOI: 10.1109/TED.2007.90696
• [2]
  Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sangwan Kim, Jong Duk Lee, and Byung-Gook Park, “Design and simulation of asymmetric MOSFETs,” IEICE Transactions on Electronics, Vol. E90-C, No. 5, pp. 978-982, May 2007. [SCIE]
  DOI: 10.1093/ietele/e90-c.5.978
• [1]
  Jae Young Song, Woo Young Choi, Jong Pil Kim, Sangwan Kim, Jong Duk Lee, and Byung-Gook Park, “Novel gate-all-around metal-oxide-semiconductor field effect transistors with self-aligned structure,” Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2046-2049, Apr. 2007. [SCI]
  DOI: 10.1143/JJAP.46.2046